Page 198 - A Practical Guide from Design Planning to Manufacturing

Chapter
6

Logic Design

Overview
This chapter discusses the process of converting a microarchitectural
design into a hardware description language (HDL) model. Validation
of the logic design model is described as well as design automation
flows, which allow HDL to be converted into layout. By hand logic min-
imization is demonstrated for combinational and sequential circuits.

Objectives
Upon completion of this chapter the reader will be able to:

1. Be familiar with the different levels of HDL abstraction.
2. Describe the trade-offs of different design automation flows.
3. Describe the goals and difficulties of pre-silicon validation.
4. Be familiar with the symbols and behavior of common logic gates.
5. Perform logic minimization of combinational or sequential circuits
using Karnaugh maps (K-maps).

Introduction
Microarchitectural choices will have the greatest impact on the proces-
sor’s performance and die area, but these choices are almost never black
and white. Microarchitecture must trade off performance with die area
and complexity. The result of the microarchitecture design is typically
block diagrams showing the interactions of the processor’s different com-
ponents and a written specification describing their algorithms. Some
simple simulations or hand calculations may be performed to estimate

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