Page 216 - A Practical Guide from Design Planning to Manufacturing

Logic Design 189

WX WX
00 01 11 10 00 01 11 10
00 0 1 0 1 00 1 0 0 1
01 0 0 0 1 01 0 1 1 0
YZ YZ
11 0 0 0 1 11 0 1 1 0
10 1 1 1 1 10 1 0 0 1
A = WXZ + WX + YZ B = XZ + XZ
Figure 6-15 Four-variable example.

maps in the same row or column. For functions of more than six vari-
ables, tabular methods are required. In summary, the general steps in
reducing a logic equation by hand are:
1. Write truth table.
2. Fill in Karnaugh map.
3. Cover all 1’s with fewest number of largest sets.
4. Write minimal sum.

There may not be a unique minimal sum. Some functions have more
than one solution with the same number of terms and inputs per term.
A good example of the process is deriving the logic for a binary add.
Each digit of a binary full adder must input three binary values: the two
numbers being added and a carry bit. The output will be a sum bit for
that digit and a carry out to go to the next digit. For binary addition, the
sum bit will be true if one or three of the inputs is true. There will be a
carry out if two or more of the inputs are true. Figure 6-16 shows the
truth table, Karnaugh maps, and minimal sums for a 1-bit full adder.

A B C C out Sum AB
00 01 11 10
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1 C
0 1 0 0 1 1 0 1 1 1
0 1 1 1 0
C out = AB + BC + AC
1 0 0 0 1
1 0 1 1 0 AB
1 1 0 1 0 00 01 11 10
1 1 1 1 1 0 0 1 0 1
C
1 1 0 1 0
Sum = ABC + ABC + ABC + ABC
Figure 6-16 1-bit full adder logic.