Page 212 - A Practical Guide from Design Planning to Manufacturing

Logic Design 185

X Y Z Fundamental X Y Z A
Product
0 0 0 X Y Z 0 0 0 1
0 0 1 X Y Z 0 0 1 0
0 1 0 X Y Z 0 1 0 1
0 1 1 X Y Z 0 1 1 0
1 0 0 X Y Z 1 0 0 1
1 0 1 X Y Z 1 0 1 1
1 1 0 X Y Z 1 1 0 0
1 1 1 X Y Z 1 1 1 0 Figure 6-7 Canonical sum.
A = XYZ + XYZ + XYZ + XYZ

Boolean algebra shows that this function could actually be implemented
with only 3 two-input gates. (See Fig. 6-8).
The simplest sum-of-products form of a function is called the minimal
sum. This is the form with the fewest and simplest terms. One of the most
important tasks of logic design is performing logic minimization to find
the minimal sum. Unfortunately this is not always straightforward.
Applying boolean algebra to try and simplify an equation can lead to dif-
ferent results, depending on in what order transformations are applied.
In this fashion, there is not a clear of way determining whether a new form
of the function is really the simplest possible. The most common way of
finding minimal sums by hand is using Karnaugh maps.

Karnaugh maps
Karnaugh maps are a graphical way of minimizing logic by allowing
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us to easily see terms that can be combined to simplify the function. The
maps work by using the concept of “neighboring” fundamental products.
Two fundamental products are considered neighbors if they differ by only
one input. Any neighboring fundamental products can be combined into
a single term. See Fig. 6-9.
Just looking at equations or a truth table, it is difficult to determine which
terms are neighbors. Karnaugh maps are tables drawn in such a way that
the results of logical neighbors are placed physically next to each other.

A = XYZ + XYZ + XYZ + XYZ
A = XZ(Y + Y) + XY(Z + Z )
A = XZ(1) + XY(1)
A = XZ + XY
Figure 6-8 Logic minimization.

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Karnaugh, “Map Method for Synthesis.”