Page 209 - A Practical Guide from Design Planning to Manufacturing

182 Chapter Six

require validation. The date when HDL must be frozen can be easily lim-
ited not by the time to implementation, but by the loss of design verifica-
tion coverage and the time to retest each HDL change.
To make design verification practical for future processors, it seems likely
more abstract models of processor behavior will be required. These could
be behavioral HDL models or new architectural description languages
(ADL). These models would try to describe the microarchitecture at a very
high level but still allow meaningful design verification. Traditional RTL
models will probably still be necessary to bridge the gap between an ADL
model and the implementation, since it is unlikely that implementation ver-
ification tools would be able to compare a behavioral model directly to
layout. There would clearly be significant added effort in maintaining sep-
arate ADL and RTL models throughout the life of a project, but the ADL
model could run quickly in simulation and be frozen early in the design.
Late changes to the RTL would be validated by comparing behavior to the
ADL model. This makes implementation verification a two-tier process.
First RTL behavior would be compared to the ADL model, and then layout
behavior would be compared to RTL. The steady growth of processor design
complexity and pre-silicon validation effort make more efficient validation
methods one of the most important needs of future processor designs.

Logic Minimization
When performed by hand the process of converting from an RTL model to
a structural model is often called logic minimization rather than logic
synthesis. Synthesis tools use libraries of cells to convert an RTL model all
the way to layout. This is fast and may provide the best solution for some
cases, but sometimes a better result can be reached by hand. Even when
automation is to be used, it is important to understand the mechanisms
behind automated synthesis. Different RTL models with the same behav-
ior can yield very different results when run through automated tools. It
helps in understanding this to be familiar with the steps of by hand logic
minimization.
The next sections make use of logic gates without discussing their cir-
cuit implementations. Chapter 7 will show how these different logic
gates are realized with actual transistors, and the real world consider-
ations of delay, noise, and power that come with real electrical circuits.
In this chapter, we consider only the logical behavior of idealized gates.

Combinational logic
The simplest types of logic are combinational logic circuits that contain
no memory. These circuits do not preserve any internal state, so the out-
puts are functions of only the inputs. An adder is a good example of com-
binational logic since the sum depends only on the two numbers being
added, not on what add instructions might have been performed earlier.