Page 206 - A Practical Guide from Design Planning to Manufacturing

Logic Design 179

Imagine you are the chief validation engineer for a processor project.
The team has been working for years and is finally ready to begin pro-
ducing the first test chips. An HDL model has been created and match-
ing circuits and layout produced for the entire design. Now you are asked
whether the entire project should move forward with the creation of the
first actual silicon chips or continue to modify the design. The essential
question is whether the current design is logically correct or not. If test
chips are produced, will they actually work? The wrong answer to this
question will cost the project time and money.
Pre-silicon validation attempts to answer this question by first check-
ing the HDL model for correctness and then checking to make sure the
implementation will match the behavior of the model. These two tasks are
called design verification and implementation verification. Design
verification relies on using the HDL model to simulate the behavior of
the processor running different programs. This behavior is compared to
the microarchitectural specification of what the behavior should be.
Usually there are also compatibility checks where the “correct” behavior
is simply what the previous generation processor did.
Without HDL models processors with today’s complexity could never be
validated and probably could never be made to function properly at all.
However, HDL models have a serious limitation. They are very, very slow.
The HDL model of a 3-GHz processor might simulate instructions at the
1
rate of a physical processor running at 1 Hz. This means that years of pre-
silicon simulation are required to test the behavior of just a few minutes
of actual operation. The design team could purchase more or faster com-
puters to perform the simulations, but this would make only a tiny differ-
ence in the vast gap between software simulation and hardware. Perhaps
with twice as many computers that are each twice as fast, the validation
team could in years of simulation duplicate the behavior of half an hour
of operation instead of just a few minutes. This still comes nowhere near
testing all the software programs that might be considered important.
To improve the speed of simulation, some projects use hardware emu-
lation. Field programmable gate arrays (FPGAs) contain logic and memory
elements that can be programmed to provide a particular behavior. By pro-
gramming FPGAs to imitate the behavior of an RTL or structural model,
the behavior of the processor might be simulated in hardware at a few
megahertz. This might be thousands of times slower than the actual
processor will run but millions of times faster than pure software simu-
lation. FPGAs were used extensively in the pre-silicon validation of AMD’s
K6 processor. 2

1
Bentley, “Validating the Intel Pentium 4,” 245.
2
Shriver and Smith, Anatomy of a Microprocessor, 28.