Page 208 - A Practical Guide from Design Planning to Manufacturing

Logic Design 181

This was how the Pentium FDIV bug escaped detection. It was actu-
ally caused by a flaw in the circuit design that was missed during imple-
mentation verification. The HDL model always yielded the correct result,
but the implementation did not exactly match the behavior of the HDL.
Behavior was identical almost all the time, but not always. To avoid these
types of escapes, implementation verification is today more commonly done
by formal equivalence checking. The HDL and circuit netlist are both con-
verted to sets of boolean equations and these are proven to be logically
equivalent. This requires far more sophisticated CAD tools but avoids the
problem of having to choose test vectors by proving that the two models will
give the same result for all possible combinations of inputs.
Logic bugs found early in the logic design process cost almost noth-
ing to fix. The HDL is simply changed to eliminate the bug. Bugs found
when the chip implementation is almost complete can become the crit-
ical path for completion of the design and delay the first prototypes. After
prototypes have been produced the cost of bugs is still higher, possibly
requiring steppings (revisions) of the design. The amount of coverage by
pre-silicon validation is one of the critical factors in determining when
to tapeout a chip design and manufacture the very first stepping. The
first stepping of a new processor almost always has bugs. This is because
pre-silicon validation can simulate only a limited number of programs
and circuit simulations are only an approximation of real behavior. It
is the job of post-silicon validation to test completed chips in order to find
and fix any bugs not found by pre-silicon validation. Finding bugs during
post-silicon validation is even more critical since finding significant flaws
after shipping has begun could lead to disastrous recalls.
Even though some bugs are expected in any first stepping, if the prob-
lems are too serious, it may be difficult to make progress with post-silicon
validation. On the other hand a design that has no logic bugs on very first
stepping may be a sign that tapeout should have been scheduled sooner.
The goal is to begin shipping as quickly as possible. The overall schedule
may be hurt by spending too much time in pre-silicon validation trying
to make the very first stepping perfect. The shortest time to market is
achieved by scheduling tapeout as soon as the design is of high enough
quality to allow effective post-silicon validation. Some bugs found before
the first design tapeout may even be left to be fixed in later steppings if
they will not pose a significant barrier to post-silicon work.
As processors have grown in complexity, pre-silicon validation has become
a more important factor in determining the overall required design time.
The number of logic bugs to be found and fixed has tended to grow linearly
4
with the number of lines of HDL code, and finding these bugs is not get-
ting any easier. Improved design automation tools allow late changes to the
HDL to be converted easily to layout, but these last minute changes still

4
Bentley, “High Level Validation Microprocessors.”