Page 378 - A Practical Guide from Design Planning to Manufacturing

348 Chapter Eleven

include a small number of unconnected logic gates scattered about the die.
By changing interconnects, a FIB edit can make use of these spare gates.
Compared to the original fabricated structure, FIB edits are extremely
crude. Adie with FIB edits would not be reliable in the long term and often
would not be able to function properly at full frequency. Editing a single
die takes hours or days. For these reasons, FIB editing could never be
used for volume manufacturing, and altered die are never sold. However,
days performing a FIB edit can demonstrate whether a proposed design
change will actually eliminate a bug without creating unintentional side
effects. This may save weeks that would be required by an extra design
stepping.
Making changes to the silicon design is slow and expensive and should
be avoided whenever possible. Most processors will include fuses that are
set to enable or disable features. These fuses set the processor clock fre-
quency and voltage, as well as turning on and off features. Some fuses may
be included specifically to allow new architectural or microarchitectural
features with high risk of bugs to be switched off. If features can be dis-
abled with some performance loss but make the die functional, this allows
the product to ship with the right fuse setting while debug continues.
Experienced design teams will intentionally add these work-arounds where
possible.
Another way some silicon bugs are fixed without changing the silicon
design is through a microcode patch. 12 Microcode instructions are low-
level steps executed by the processor when performing complex instruc-
tions, dealing with unusual events, or to initialize the processor during
reset. Because microcode flows perform some of the most complex opera-
tions, they are likely to contain bugs. The microcode instructions are hard-
wired into a read-only memory (ROM) on the processor die. However, some
processors are designed with the ability to “patch” the microcode. Every
time the processor turns on, the reset microcode flow checks to see if a
microcode patch has been loaded into flash memory on the motherboard. If
so, the processor loads this patch into a RAM array that sits next to the
microcode ROM on the processor die. Each time the microcode ROM is
accessed, the patch RAM is checked to see if a new version of the microc-
ode flow is available for that particular function. Running the patch can cor-
rect bugs caused by errors in the microcode ROM or allow new microcode
flows to work around other bugs in the design.
Updates to the motherboard BIOS are also used to avoid some bugs.
The BIOS is a ROM array that contains initialization flows and functions
for dealing with special operations on the motherboard the same way the
microcode ROM stores similar routines for the microprocessor. Storing the

12
Sherwood and Brad, “Patchable Instruction ROM Architecture.”