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50   Chapter Two

          The double data rate SDRAM (DDR SDRAM) standard provides more
        bandwidth by supplying two pieces of data per memory bus clock in
        burst mode instead of just one. This concept has been extended by the
        DDR2 standard that operates in the same fashion as DDR but uses dif-
        ferential signaling to achieve higher frequencies. By transmitting data
        as a voltage difference between two wires, the signals are less suscepti-
        ble to noise and can be switched more rapidly. The downside is that two
        package pins and two wires are used to transmit a single bit of data.
          Rambus DRAM (RDRAM) achieves even higher frequencies by plac-
        ing more constraints on the routing of the memory bus and by limiting
        the number of bits in the bus. The more bits being driven in parallel,
        the more difficult it is to make sure they all arrive at the same moment.
        As a result, many bus standards are shifting toward smaller numbers
        of bits driven at higher frequencies. Some typical memory bus stan-
        dards are shown in Table 2-4.
          To make different DRAM standards easier to identify, early SDRAM
        standards were named “PC#” where the number stood for the bus fre-
        quency, but the advantage of DDR is in increased bandwidth at the same
        frequency, so the PC number was used to represent total data band-
        width instead. Because of the confusion this causes, DDR and DDR2
        memory are often also named by the number of data transfers per second.
          Just as with processor buses, transfers per cycle and clocks per cycle
        are often confused, and this leads to DDR266 being described as 266-MHz
        memory even though its clock is really only half that speed. As if things
        weren’t confusing enough, the early RDRAM standards used the PC
        number to represent transfers per cycle, while later wider RDRAM bus
        standards have changed to being labeled by total bandwidth like DDR
        memory.




        TABLE 2-4  Memory Bus Standards
                                Bus   Memory            Transfers  Max data
                               width  bus clock  Transfers  per second  bandwidth
              Memory bus        (b)    (MHz)   per clock  (MT/s)   (MB/s)
        PC100 SDRAM              64     100      1        100       800
        PC133 SDRAM              64     133      1        133      1066
        PC2100 DDR (DDR266)      64     133      2        266      2133
        PC2700 DDR (DDR333)      64     167      2        333      2667
        PC2-3200 DDR (DDR2-400)  64     200      2        400      3200
        PC2-4300 DDR2 (DDR2-533)  64    267      2        533      4267
        PC800 RDRAM              16     400      2        800      1600
        PC1066 RDRAM             16     533      2       1066      2133
        PC3200 RDRAM             32     400      2        800      3200
        PC4200 RDRAM             32     533      2       1066      4267
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