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Control Approaches for Parallel Source Converter Systems 207

The purpose of the arbitrary small value β in (5.263) is to introduce a
hysteresis band with the boundary conditions. By doing so, it provides a
form of control to the switching frequency of the converter. This method
alleviates the chattering effect of SM control. With this choice of the
control law, the operation is so that if the parameters of the state variables
are such that σ(x) . β, the switch of the buck converter will turn on.
Conversely, it will turn off when σ(x) ,2 β. In the region
2 β , σ(x) , β, the switch remains in its previous state. Therefore, the
introduction of a no-switching region 2 β , σ(x) , β allows the maxi-
mum switching frequency of the SM controller to be controlled, which
alleviates the effect of chattering. Furthermore, it is possible to control
the frequency of the operation by varying the magnitude of β.
In a practical converter control, only the inductor current I and the
output voltage V are sensed. Generation of current reference and voltage
reference is needed to implement the following manifold:

s 5 V 2 V ref 1 k I 2 I ref (5.264)
In practice, generation of reference inductor current signal is challeng-
ing, since it depends on the converter operating point (output power and
input voltage). Classically, the reference signal is usually derived directly
from the inductor current by using a low pass [77].

5.8.5 Simulation Results
In our simulation examples we use a slightly different approach than in
the previous example. For the Cascaded System and ISPS we use the state
I d which is the so-called disturbance current. This disturbance current is
estimated by the Kalman filter in the framework of the virtual distur-
bance. The resulting manifold is described by:

(5.265)
s 5 V 2 V ref 1 kUI d

5.8.5.1 Cascaded System
A cascaded converter setup has been modeled in Matlab-SIMULINK
with the parameters described in Table 6.1. In the simulation, a step vari-
ation of the CPL load has been performed. The variation of the bus volt-
age during the step change of the CPL load is described in Fig. 5.67 At