Page 132 - Phase-Locked Loops Design, Simulation, and Applications
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MIXED-SIGNAL PLL ANALYSIS   Ronald E. Best                                              84

               If, in an FM system, the PLL is pulled out by too large a frequency step, we can expect that
               PLL to return to stable operation—by means of a relatively slow pull-in process—provided
               the frequency offset Δω = ω  − ω ′ is smaller than Δω . If the corresponding pull-in time is
                                          1
                                                                      P
                                                0
               considered to be too long, the peak frequency deviation Δω must be confined to the lock range
               Δω .
                  L
                 Phase detector type 2. When the EXOR phase detector is chosen, the pull-out range also is
               the frequency step that causes the pendulum in the model of Fig. 3.7 to tip over. With the
               EXOR phase detector, the average output signal     versus phase error is a triangular function,
               as shown in  Fig. 2.7. Because this is a nonlinear function, it is not possible to calculate
               explicitly the pull-out frequency. Using the PLL design program distributed with this book,
               the pull-out range was determined by simulation, using damping factors in the range 0.1 < ζ <
               3. Then, a least-squares fit gave the approximation


                                                                                           (3.89)


               As could be expected, this result is not far from that for phase detector type 1.
                 Phase detector type 3. A different procedure is used to compute the pull-out range of the
               PLLs using a JK-flipflop or a PFD as phase detector. In the case of the JK-flipflop, the pull-
               out range is the frequency step causing the peak phase error to exceed π. Because the average
               output signal     of the JK-flipflop actually is linear in the range −π < θ  < π, the pull-out
                                                                                        e
               range can be computed explicitly. Using the linear model of the PLL (Fig. 3.1), phase error θ
                                                                                                         e
               is calculated for a frequency step Δω applied to the reference input. The result is a damped
                          1
               oscillation.  Using the rules of  differential calculus, it is straightforward to calculate the
               maximum of the phase error. From there, it is quite easy to calculate the size of the frequency
               step that leads to a peak phase error of π. Assuming the PLL is a high-gain loop, we get



                                                                                           (3.90)









               If Δω    is plotted against ζ, we notice that the curve becomes rather flat and could easily be
                     PO
               replaced by a linear function. This would ease the computation of the pull-out range
               considerably, because tables for inverse hyperbolic tangent, for  example, are not always at
               hand. A least-squares fit performed with Eq. (3.90) gave the approximation



                                                                                           (3.91)

                 Phase detector type 4. The following analysis is valid for both voltage- and current-output
               PFDs, because the normalized phase-transfer function H(s) is the same
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