Page 130 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 83
have seen, the pull-in range cannot be larger than the range of frequencies the VCO is able to
create. However, there is another, even more stringent, restriction. When phase detector type 1
or 2 is used, the PLL can false-lock onto a harmonic of the reference frequency. To explain
that phenomenon, we’ll use two examples.

Example 1 Consider a PLL with type 1 phase detector (multiplier) and no down scaler. Let
the center frequency be f = 100 kHz. Assume that the reference frequency is f = 100 kHz
0 1
initially. Now the reference frequency suddenly jumps to 50 kHz. We would expect the VCO
to pull down its frequency to 50 kHz, but it remains locked at 100 kHz. What happened?
With f = 100 kHz and f = 50 kHz the multiplier generates the sum and difference of these
1 2
two frequencies—for instance, 150 kHz and 50 kHz. The frequency of the VCO is thus
modulated by a 50 kHz and a 150 kHz component. The frequency modulation generated by
the 50 kHz component creates sidebands at 50 kHz and 150 kHz. The lower sideband (50
kHz) has exactly the reference frequency, which causes the phase detector to output a DC
signal, which depends on the phase shift between these two 50 kHz signals. The phase
detector therefore “believes” that the PLL is perfectly locked, but in effect it is locked to
twice the reference frequency.

Example 2 Consider a PLL with type 2 phase detector (EXOR) and no down scaler. Again,
the center frequency is f = 100 kHz. The reference frequency f is assumed to be 100 kHz
0
1
initially. Now f suddenly jumps down to 40 kHz. We would expect the VCO to pull down
1
its frequency to 40 kHz as well, but it ramps up to 120 kHz and stays locked there! What
happened? The PLL locked onto the third harmonic of the reference frequency. In effect, the
reference signal, which is assumed to be a symmetrical square wave has odd harmonics—in
other words, third, fifth, and so on. The third harmonic is 120 kHz. When the VCO oscillates
at 120 kHz, the EXOR phase detector thinks the PLL is perfectly locked. Indeed, it is locked,
but on the wrong frequency.

It shows up that the full pull-in range can only by realized when either type 3 or type 4
phase detectors are chosen. Because phase detector type 4 is not only phase- but also
frequency-sensitive, the pull-in process is much faster if type 4 is selected.

Pull-out range Δω PO

Phase detector type 1. The pull-out range is, by definition, the frequency step that causes a
lock-out if applied to the reference input of the PLL. In the mechanical analogy of Fig. 3.7, the
pull-out frequency corresponds to the weight that causes the pendulum to tip over if the weight
is suddenly dropped onto the platform.
An exact calculation of the pull-out range is not possible for the linear PLL. However,
6
simulations on an analog computer have led to an approximation:

(3.87)

In most practical cases, the pull-out range is between the lock range and the pull-in range

(3.88)