Page 147 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 91
the loop will not lock out in the fifth cycle. Because the actual phase error is only a fraction
K of the phase error that would be seen without CSR, this reduces the detector gain to
CSR

This implies that the loop gain is decreased, and the natural frequency ω is reduced to
n
. Consequently, the loop will lock slower by a factor .
To avoid this drawback, we can combine CSR with fastlock. When doing so, the resulting
detector gain becomes

This equation tells us that the PLL locks faster by a factor of . This implies that

the product K · K must be made larger than 1 in order to get faster acquisition. We
FL CSR
could, for instance, choose K = 16 and K CSR = 1/4 to have K P,comb four times larger than
FL
the initial K . When using fastlock in combination with CSR, we would have to select resistor
P
*
*
R in Fig. 3.20 such that the parallel connection of R and R becomes
2
2
2

.
In-Lock detectors

We saw in Sec. 3.10 that switching the filter resistor R 2 * and the comparison frequency in

frequency synthesizers requires an in-lock detector. An in-lock detector is a logical circuit
having a binary output that tells us whether or not the PLL has acquired lock. Many different
schemes are used to implement in-lock detectors. One simple method is depicted in Fig. 3.21.
This principle is utilized in National’s frequency synthesizer IC type LMX2470. 54 To
check if the PLL is locked, the in-lock detector measures the time difference between two
consecutive positive transitions of the u and u ′ signals (input signals to the phase detector).
1
2
The loop is decided to be in lock when this time difference is less than 15 ns in five
consecutive reference cycles (cycles of the u signal). Whenever a time difference larger than
1
15 ns is found, the logical output of the in-lock detector is set low.

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