Page 144 - Phase-Locked Loops Design, Simulation, and Applications
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MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 90
where K can take the values 1, 1/2, 1/3, and so on. Actually, we do not evaluate the phase
CSR
error in every reference cycle, only at a lower frequency f comp . When we set K CSR = 1/4, for
example, and the phase error attains the value 2π in the fourth reference cycle, the phase error
referred to the reduced comparison frequency becomes four times less—in other words, only
π/2. Under these conditions,
