Page 179 - Phase-Locked Loops Design, Simulation, and Applications

DESIGN PROCEDURE FOR MIXED-SIGNAL PLLS Ronald E. Best 110
mandatory to define more than one frequency range for the PLL and switch the range
accordingly. To ease the design in the case of variable N, we specify the parameters of the
PLL such that ζ becomes optimum for a divider ratio N mean , which is given by the geometric
mean of N and N ,
max min

(5.3)

(For constant N, N mean = N, of course.) If N min = 10 and N max = 100, for example, N mean

would be 31.6 → 32. Choosing ζ = 0.7 for N = 32 would yield a minimum damping factor of
ζ = 0.4 and a maximum of ζ = 1.2, which is a fair compromise.
min max
Step 3. Determination of damping factor ζ. When N is constant, ζ remains constant, too, and
can be chosen arbitrarily. For constant N, it is optimum to select ζ = 0.7; the PLL then has a
Butterworth response, as explained in Sec. 3.3.1. If N is variable, however, it is recommended
to choose ζ = 0.7 for N = N , as explained in step 2.
mean
Step 4. In this step, the question must be answered as to whether the PLL should offer noise
suppression or not. If a digital frequency synthesizer must be built, for example, noise can be
discarded, and parameters such as noise bandwidth B must not be considered. If noise must
L
be suppressed, however, B and related parameters must be taken into account. If noise is of
L
concern, the procedure continues at step 5, otherwise at step 12.
Step 5. Noise must be suppressed by this PLL. As discussed in Sec. 4.3, the various digital
phase detectors behave differently in the presence of noise. In a situation where edges of the
reference (input) signal u can get lost, edge-sensitive phase detectors such as the JK-flipflop
1
or the PFD then can hang up in one particular state: the output of the JK-flipflop will switch
into the “low” state, and the output of the PFD will switch to the state −1 after a very short
time. Consequently, the frequency of the VCO will run away quickly, which is certainly
undesirable. The average output signal u of the EXOR phase detector, however, will stay at 0
d
when edges of u are missing. Another option would be the multiplier phase detector, because
1
this detector is also level-sensitive and performs similarly to the EXOR. If edges of u are
1
likely to get lost, the procedure continues at step 6, otherwise at step 7.

Step 6. The EXOR phase detector (or the multiplier) should be selected. In case of the
multiplier PD, the detector gain must be taken from the data sheet of the corresponding device.
When the EXOR is chosen and runs from a unipolar power supply, K is given by K = U /π,
d
d
B
where U is the supply voltage. When a bipolar power supply is used, or when the EXOR
B
saturates at levels that differ substantially from the power-supply rails, use Eq. (2.19). The
procedure continues with step 8.
Step 7. The JK-flipflop or the PFD can be chosen for the phase detector. As explained in
Sec. 2.4.4, the PFD offers superior performance—for example, infinite

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