Page 190 - Phase-Locked Loops Design, Simulation, and Applications

DESIGN PROCEDURE FOR MIXED-SIGNAL PLLS Ronald E. Best 116
moment that the series capacitor C has a very high value; thus, the varactor capacitance
S
appears in parallel to the capacitance of the series connection of C and C . Let
1
2
, then the total capacitance of the tank circuit becomes C + C , where C is the
V V
capacitance of the varactor. The component values are now chosen such that the oscillator
generates the output (radian) frequency ω 2min when the loop filter output voltage is u fmin , and
the output frequency is ω when u = u . For u = u , the varactor capacitance is
2max f fmax f fmin
supposed to be C vmax , while for u = u fmax , the varactor capacitance is supposed to be C vmin .
f
Afterward, the maximum output frequency is determined by

(5.6)

and the minimum output frequency is

(5.7)

Afterward, the ratio of maximum to minimum output frequency is given by

(5.8)

Generally, these ratios are close to 1—for example, 1.01. This means the var-actor
capacitance is small compared with capacitance C. Introducing the variables Δω = ω −
2 2max
ω 2min and ΔC = C vmax − C vmin , we have approximately
V

(5.9)

Now we introduce the relative quantities , and get the

expression

(5.10)

Because the relative quantities are much smaller than 1, we can apply a Taylor series
expansion to Eq. (5.10) and finally get

(5.11)