Page 186 - Phase-Locked Loops Design, Simulation, and Applications

DESIGN PROCEDURE FOR MIXED-SIGNAL PLLS Ronald E. Best 114
Step 15. Determination of dynamic properties of the PLL. To select an appropriate value for
the natural frequency ω , we must have an idea of how the PLL should react to dynamic
n
events, for example, on frequency steps applied to the reference input, on a variation of the
divider factor N, or the like. Specification of dynamic properties strongly depends on the
intended use of the PLL system. Because different goals can be envisaged, this design step is a
decision block having three outputs—in other words, you can specify dynamic performance of
the PLL in three different ways.
In the first case, the PLL is used as a digital frequency synthesizer. Here, it could be
desirable that the PLL switches very quickly from one output frequency f to another output
21
frequency f . If the difference |f − f | is large, the PLL will probably lock out when
22
22
21
switching from one frequency to the other. The user then would probably specify a maximum
value for the pull-in time T the system needs to lock onto the new output frequency. T is
P
P
then used to determine the remaining parameters of the PLL. If the user decides to specify T
P
as a key parameter, the procedure continues at step 16.
In the second case, the PLL is also used as a digital frequency synthesizer. This synthesizer
will generate integer multiples of a reference frequency that is, the frequency at the
output of the VCO is given by f = N · f , where N is variable. In many synthesizer
ref
2
applications, it is desired that the PLL does not lock out if the output frequency changes from
one frequency “channel” to an adjacent “channel,”—that is, if f changes from N · f ref
0
2
to (N + 1) · f . In this case, the pull-out range Δω PO is required to be less than f . If the
ref
ref
0
user decides to use Δω PO as a key parameter, the procedure continues at step 20.
The third case of this decision step represents the more general situation where neither the
pull-in time nor the pull-out range is of primary interest. Here the user must resort to a
specification that makes as much sense as possible. Probably the simplest way is to make an
assumption on the lock-in time T (also referred to as settling time) or even to specify the
L
natural frequency immediately. If the third case is chosen, the design proceeds with step 21.
Step 16. When the voltage output PFD is used, the sum of both time constants τ + τ of the
2
1
loop filter is computed from the equation for T in Table 3.4. For Δω , the maximum (radian)
0
P
frequency step at the VCO output must be entered.
When the current output PFD is used, we will compute the value of capacitor C from the
1
equation for T in Table 3.5. For Δω , the maximum (radian) frequency step at the VCO
P 0
output must be entered as well. The design proceeds with step 17.
Step 17. When the voltage output PFD is used, the natural frequency ω is now computed
n
from the sum τ + τ using the equation for ω in Table 3.4. When the current output PFD is
1 2 n
used, however, we will calculate the natural frequency ω from the known parameters K , K ,
P
0
n
N, and C , using the equation for ω in Table 3.5. The design proceeds with step 18.
1 n
Step 18. First we describe the design procedure for the case where the voltage output PFD
is used. Given ω and ζ now, time constant τ is calculated using
n 2