Page 224 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL APPLICATIONS PART 1: INTEGER-N FREQUENCY
SYNTHESIZERS Ronald E. Best 136
■ As we have seen in Sec. 2.4, the phase detector delivers an output signal that is
proportional to the phase error θ of the loop. This signal is a “quasi-DC” signal. In
e
addition, the phase detector creates AC components at higher frequencies. Depending on
the type of phase detector chosen, there may be an AC signal component at the reference
frequency or at twice the reference frequency, which is the case for the EXOR. As we will
see later in this section, in the case of the PFD with voltage output there can be even an AC
component which is a subharmonic of the reference frequency. These unwanted AC
components are partially suppressed by the loop filter, but the residual signal still will
frequency-modulate the VCO output. When the frequency of that AC signal is equal to the
reference frequency f , for example, we will observe “spurs” at a distance of ±f , ±
ref
ref
2f … from the carrier frequency f . The signal causing those spurs is denoted u (ft =
ref 0 ft
feedthrough) in Fig. 6.14.
All these noise sources contribute to output phase jitter (labeled θ n,out in Fig. 6.14) and
spurious sidebands. This all may sound disappointing, but when we succeed in quantifying the
sources of trouble, we are in a position to minimize the undesired disturbances. In the
following, we therefore analyze the three mentioned effects.

Phase noise created by the reference oscillator

To analyze phase noise at the output of the reference oscillator, let us recall the noise theory
presented in Sec. 4.3. Figure 4.4 has shown the relationships between signal power P , noise
s
power P , and input phase jitter θ . In Fig. 4.4a, the power spectral density (PSD) of noise
n
n1
power P was shown. This power spectrum has one-sided bandwidth B /2 and is symmetrical
n i
around the center frequency f of the PLL. Figure 4.4b represented the PSD of input phase
0
jitter θ . This spectrum also has the one-sided bandwidth B /2 and is symmetrical around f =
n1
i
0. The input phase jitter has been shown to modulate the phase of the carrier frequency f 0
(center frequency of the PLL). This was described by

(6.4)

[cf. Eq. (2.2)]. For the following analysis we will use the phase noise model shown in Fig.
6.15. The superposition of phase noise is accomplished by a phase modulator (PM). The phase
noise θ (t) modulates the phase of the carrier having signal power P . The phase modulator is
s
n1
followed by a unity gain amplifier that is assumed for the moment to be noiseless.
When the input phase jitter contains a component at frequency f , we saw that this gives
m
rise to two sidebands in the power spectrum P (Fig. 4.4a), one line being at frequency f + f ,
m
0
n
the other at f − f . Therefore, the spectra of input phase jitter and noise power are offset from
0 m
each other by the carrier frequency f .
0
Equation (4.1) gave the relationship

(6.5)