Page 361 - Satellite Communications, Fourth Edition

Error Control Coding 341

where p(r/1) is the probability of receiving value r, given that a 1 was
transmitted and p(r/0) the probability of receiving value r, given that a
0 was transmitted. If the voltage levels are normalized so that 1V rep-
resents a probability of 1, a certainty and 0V, zero probability, then for
r 0.9V for example, p(r/1) 0.9 and p(r/0) 1 .9 0.1, so that LLR
2.197. With r 0.3, LLR 0.847. In general, LLR yields a positive
number for r closer to 1 and a negative number for r closer to 0. The
magnitude of LLR is a measure of “how close.” These two pieces of infor-
mation are included in the soft sequences that form a part of the output
of the multiplexer and which is the input to the decoders. The outputs
from the decoders are also “soft” and the system is referred to as soft-
input soft-output (SISO).
As shown in Fig. 11.12, the switches are in position 1 for the first
iteration of the decoding step. Following the first iteration the switches
are switched to position 2, and each decoder makes use of the soft
information obtained from the other decoder to obtain a better estimate
of bit values. Recall that two independent parity sequences are avail-
able for a given data sequence. The decoded data is adjusted to take
into account the new estimates, and the process is repeated a number
of times, typically for 4 to 10, before a final hard decision is made. The
information that is obtained from the received data bits is termed
intrinsic information, the intrinsic information flow paths being shown
by the solid line in Fig. 11.12. The information that is passed from
one decoder to the other is termed extrinsic information, the paths
for the extrinsic information flow being shown by the dotted line.
After the final iteration the output of the second decoder is switched
to the output line (not shown in Fig. 11.12). It will be a 1 for a positive
LLR and a 0 for a negative LLR. A more detailed description of the
encoder of Fig. 11.11 and the decoder of Fig. 11.12 will be found in
Burr (2001).

11.11.1 Low density parity check (LDPC)
codes
LDPC refers to the fact that the parity check matrix (Sec. 11.2) is sparse,
that is, it has few binary 1s compared to binary 0s. The LDPC codes were
first introduced by Gallagher (1962) who showed that a low density
parity check matrix resulted in excellent minimum distance properties
(as defined in Sec. 11.2), and they are comparatively easy to implement.
As mentioned above a feature common to LDPC codes and turbo codes
is that SISO decoding is employed, and a series of iterations performed
to (hopefully) improve the probability estimate of a bit being a 1 or 0.
Only after a predetermined number of iterations is a “hard decision”
arrived at.