Page 115 - The Art and Science of Analog Circuit Design

One Trip Down the 1C Development Road

The last step in the circuit design is rechecking and/or optimizing the
area of every transistor. This is usually done by checking the circuit's
performance over temperature. I always add a little extra area to the tran-
sistors that are running close to saturation when the additional parasitic
capacitance won't hurt anything.

Mask Design

Experienced analog 1C designers know how important 1C layout is. Tran-
sistors that are supposed to match must have the same emitter size and
orientation as well as the same temperature. The fader output amplifier is
capable of driving a cable and generating significant thermal gradients in
the 1C. For this reason I put both input stages on one end of the die next
to the current steering devices and put the output stage at the other end.
The bias circuits and the control op amps went in the middle. The best
way to minimize thermal feedback is distance. The 14-pin SO package
set the maximum die size and the pad locations.
The 1C process used had only one layer of metalization and therefore I
provided the mask designer with an estimate of where "cross-unders"
would be needed. For those of you not familiar with the term "cross-
under," I will explain. A cross-under is a small resistor, usually made of
N+, inserted in a lead so that it can "cross-under" another metal trace.
Normally these cross-unders are inserted in the collectors of transistors,
since a little extra resistance in the collector has minimal effect.
The fader circuit, with over 140 transistors and very few resistors, was
clearly going to have a lot of cross-unders. I was resigned that both sup-
plies would have many cross-unders; in order for the circuit to work prop-
erly, the voltage drops introduced by the cross-unders must not disturb the
circuit. For example, the current mirrors will common mode out any vari-
ation in supply voltage as long as all the emitters are at the same voltage.
This is easy to do if the emitters all connect together on one trace and
then that trace connects to the supply. As mask design progresses, it is
important that each cross-under added to the layout be added to the
schematic and that circuit simulation is re-checked. Time spent before the
silicon comes out to insure that the circuit works is well spent.
I would like to make a comment or two on mask design and the time
that it takes. For as long as I can remember, speeding up mask design has
been the Holy Grail. Many, including myself, have thought that some new
tool or technique will cut the time required to layout an 1C significantly.
When computer layout tools became available, they were sold as a pro-
ductivity enhancement that would cut the time it takes to layout ICs. The
reality was that the ICs became more complex and the time stayed about
the same.
The analog ASIC concept of a huge library of functions available as
standard cells that are just plopped down and hooked up sounds great;
except that very few innovative products can be done with standard func-

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