Page 116 - The Art and Science of Analog Circuit Design

William H Gross

lions. What typically happens is that each new product requires modifica-
tions to the "standard" cells or needs some new standard cells. You're
right back at transistor level optimizing the 1C. Of course no one ever
plans for the extra time that this transistor level optimization takes, so the
project gets behind schedule.
The "mono-chip" or "master-chip" idea is often used to speed up de-
velopment. This technique uses just the metal layer(s) to make the new
product; a large standard 1C with many transistors and resistors is the
common base. The trade-off for time saved in mask design is a larger die
size. The argument is often made that if the product is successful, a full
re-layout can be done to reduce die size and costs. Of course, this would
then require all the effort that should have been done in the first place. I
would not argue to save time and money up front because I did not ex-
pect my part to be successful!
In summary, mask design is a critical part of analog 1C development
and must be considered as important as any other step. Doing a poor job
of mask design will hurt performance and that will impact the success of
a product much more than the extra time in development.

Testing

1C automatic test system development is an art that combines analog
hardware and software programming. We cannot sell performance that
we cannot test. It is much easier to measure 1C performance on the bench
than in an automatic handler. In successful companies, the good test de-
velopment engineers are well respected.
The fader 1C requires that the closed loop AC gain be measured very
accurately. The gain is trimmed at wafer sort by adjusting the value of
resistor R C. This trim is done with the control input fixed and the linearity
of the circuit determines the gain accuracy elsewhere. The errors due to
the bulk resistance of the steering transistors have no effect at 50% gain;
therefore it seemed like the best place to trim the gain.
While characterizing the parts from the first wafer, I noticed that there
were a few parts that had more error than I expected at 90% gain. I also
determined that these parts would be fine if I had trimmed them at 90%.
It was also true that the parts that were fine at 90% would not suffer from
being trimmed at 90%. So, I changed my mind as to where the circuit
was to be trimmed and the test engineer modified the sort program. More
wafers were sorted and full characterization began.
Setting the data sheet limits is a laborious process that seems like it
should be simpler. The designer and product engineer go over the distri-
bution plots from each test to determine the maximum and minimum
limits. In a perfect world we would have the full process spread repre-
sented in these distributions. Even with a "design of experiments" run that
should give us the full spread of process variations, we will come up short
of information. It's Murphy's law. This is where the designer's knowledge