Page 78 - The Art of Designing Embedded Systems

Real Time Means Right Now! 65

to the CPU. If you were clever enough to fill the vector table’s unused en-
tries with pointers to a null routine, watch for a breakpoint on that function.
You may have misprogrammed the table entry or the interrupt controller,
which would then supply a wrong vector to the CPU.
If the program vectors to the wrong address, then use a logic analyzer
or emulator’s trace to watch how the CPU services the interrupt. Trigger
collection on the interrupt itself, or on any read from the vector table in
RAM. You should see the interrupt controller drop a vector on the bus. Is
it the right one? If not, perhaps the interrupt controller is misprogrammed.
Within a few instructions (if interrupts are on) look for the read from
the vector table. Does it access the right table address? If not, and if the
vector was correct, then either you’re looking at the wrong system inter-
rupt, or there’s a timing problem in the interrupt acknowledge cycle. Break
out the logic analyzer and check this carefully.
Hit the databooks and check the format of the table’s entries. On an
x86-style processor, four bytes represent the ISR’s offset and segment ad-
dress. If these are in the wrong order-and they often are-there’s no
chance your ISR will execute.
Frustratingly often the vector is fine; the interrupt just does not occur.
Depending on the processor and peripheral mix, only a handful of things
could be wrong:
Did you enable interrupts in the main routine? Without an E1 in-
struction, no interrupt will ever occur. One way of detecting this is
to sense the CPU’s INTR input pin. If it’s asserted all of the time,
then generally the chip has all interrupts disabled.
Does your I/O device generate an interrupt? It’s easy to check this
with external peripherals.
Have you programmed the device to allow interrupt generation?
Most CPUs with internal peripherals allow you to selectively dis-
able each device’s interrupt generation; quite often you can even
disable parts of this (such as allow interrupts on “received data”
but not on “data transmitted”).
Modern peripherals are often incredibly complex. Motorola’s TPU,
for example, has an entire book dedicated to its use. Set one bit in one reg-
ister to the wrong value, and it won’t generate the interrupt you are look-
ing for.
It’s not uncommon to see an interrupt work perfectly once, and then
never work again. The only general advice is to be sure your ISR reenables
interrupts before returning. Then look into the details of your processor
and peripherals.