Page 74 - The Art of Designing Embedded Systems

Real Time Means Right Now! 61

ing for processor time. Save overhead by making the ISR read the FIFOs
until the EMPTY flag is set. You’ll have! to connect the EMPTY flag to a
parallel port so the software can read it, but the increase in performance is
well worth it.
In mission-critical systems it might also make sense to design a sim-
ple circuit that latches the combination of FULL and an incoming new data
item. This overflow condition could be disastrous and should be signaled
to the processor.
A few bucks invested in a FIFO may allow you to use a much slower,
and cheaper, CPU. Total system cost is the only price issue in embedded
design. If a $5 %bit chip with a $6 FIFO does the work of a $20 16-bitter
with double the RAM/ROM chips, it’s foolish to not add the extra part.
Figure 4-5 shows the result of an Intel study of serial receive interrupts
coming to a 386EX processor. At 530,000 baud-or around 53,000 charac-
ters per second-the CPU is almost completely loaded servicing interrupts.
Add a 16-byte FIFO and CPU loading declines to a mere 10%. That’s
a stunning performance improvement!

C or Assembly?

If you’ve followed my suggestions, you have a complete interrupt
map with an estimated maximum execution time for the ISR. You’re ready
to start coding . . . right?
If the routine will be in assembly language, convert the time to a
rough number of instructions. If an average instruction takes x microsec-
onds (depending on clock rate, wait states, and the like), then it’s easy to
get this critical estimate of the code’s allowable complexity.

100 12

80 10
8 0 9600
60 0 38400
6 0 57600
40
4 rn 115200
rn 230400
20 2
0 0
FIGURE 4-5 Baud rates versus CPU utilization. On the left, a con-
ventional connection uses 90% of the CPU to service 530k baud inputs.
On the right, with a FIFO the processor is 10% loaded at the same rate.