Page 73 - The Art of Designing Embedded Systems

60 THE ART OF DESIGNING EMBEDDED SYSTEMS

The biggest issue is the generation of the INTR signal itself. Don’t sim-
ply pulse an interrupt input. Though some chips do permit edge-triggered in-
puts, the vast majority of them require you to assert and hold INTR until the
processor issues an acknowledgment, such as from the interrupt ACK pin.
Sometimes it’s a signal to drop the vector on the bus; sometimes it’s nothing
more than “Hey, I got the interrupt-you can release INTR now.”
As always, be wary of timing. A slight slip in asserting the vector can
make the chip wander to an erroneous address. If the INTR must be exter-
nally synchronized to clock, do exactly what the spec sheet demands.
If your system handles a really fast stream of data, consider adding
hardware to supplement the code. A data acquisition system I worked on
accepted data at a 20-microsecond rate. Each generated an interrupt, caus-
ing the code to stop what it was doing, vector to the ISR, push registers
like wild, and then reverse the process at the end of the sequence. If the
system was busy servicing another request, it could miss the interrupt al-
together.
A cheap 256-byte-deep FIFO chip eliminated all of the speed issues.
The hardware filled the FIFO without CPU intervention. It generated an in-
terrupt at the half-full point (modem FIFOs often have Empty, Half-Full,
and Full bits), at which time the ISR sucked data from the FIFO until it was
dry. During this process additional data might come along and be written
to the FIFO, but this happened transparently to the code.
Most designs seem to connect FULL to the interrupt line. Conceptu-
ally simple, this results in the processor being interrupted only after the en-
tire buffer is full. If a little extra latency causes a short delay before the
CPU reads the FIFO, then an extra data byte arriving before the FIFO is
read will be lost.
An alternative is EMPTY going not-true. A single byte arriving will
cause the micro to read the FIFO. This has the advantage of keeping the
FIFOs relatively empty, minimizing the chance of losing data. It also
makes a big demand on CPU time, generating interrupts with practically
every byte received.
Instead, connect HALF-FULL, if the signal exists on the FIFOs
you’ve selected, to the interrupt line. HALF-FULL is a nice compromise,
deferring processor cycles until a reasonable hunk of data is received, yet
leaving free buffer space for more data during the ISR cycles.
Some processors do amazing things to service an interrupt, stacking
addresses and vectoring indirectly all over memory. The ISR itself no
doubt pushes lots of registers, perhaps also preserving other machine in-
formation. If the HALF-FULL line generates the interrupt, then you have
the a priori information that lots of other data is already queued and wait-