Page 1193 - The Mechatronics Handbook

Resistive Networks

Resistive networks in a DAC provide the varying levels of analog output voltage, which will form the
output of the DAC. Although many different resistive schemes are used in DAC design, the basic principle
is common in all of them. The one shown in Fig. 46.5 uses a dual resistor quad approach. In the figure,
bits 0–3 and 4–7 are separated by a single resistor. These two independent groups are each a resistor
quad with resistor values of 1R-2R-4R-8R where R is equal to 10 kWs. If any of the switches is in the 1
position, a current will develop across the resistor proportional to the resistors’ value. Therefore, if bit 0
is on a current proportional to 1/1R is generated, whereas if switch 2 is on a current proportional to
1/4R would be generated. The resistor between the two quads has the effect of a 16:1 current attenuator,
so that even though bit 4 would generate a current proportional to 1/1R, once it gets to the amplifier it
would appear to have a current proportional to 1/16R. In this case, bit 0 would be the most significant
bit (MSB), and bit 7 would be the least significant bit (LSB).

Summing Amplifier
The operational amplifier (op-amp) used in the DAC circuit of Fig 46.5 is acting as a summing amplifier.
As the different bits generate a particular current, the op-amp is designed to collect the total current and
would generate an output voltage. This output voltage of the op-amp is now an analog representation
of the digital code which was fed to the DAC.

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