Page 135 - Troubleshooting Analog Circuits

I22 IO. The Analog/Digital Boundary

mediocre amplifier this way, but when the supply voltage is above 6 V, the power
drain gets pretty heavy and the gain is low. I don’t recommend this approach for
modem designs.
Many years ago, people used to tie the outputs of DTL or open-collector TTL gates
together to form a “wired OR’ gate. This practice has fallen into disrepute as it sup-
posedly leads to problems with troubleshooting. I don’t know what other reason there
is for not doing it, except to avoid acting like a nerd. However, an open-collector out-
put with a resistive pull-up is slower than a conventional gate and wastes more power.
A couple engineers chided me, that if you let TTL or DTL inputs float, that may
appear to work OK for a while, but when you get all the signal busses packed in
together, the unused inputs may be driven to give a false response-not consistently
but intermittently. So, it is bad practice to let your lTL inputs float. It is also not quite
correct to tie those inputs to the +5-V bus. Tie them up toward +5 V through 1 k.
Then a momentary +7-V transient on the supply bus may do less harm, less damage.
When digital-circuit engineers have to drive a bus for a long distance, say 20 or 30
inches, they use special layouts, so the bus will act like a 75 Q or 93 Q stripline.
They also add termination resistors at one or both ends of the bus to provide damping
and to cut down on reflections and ringing. When you have to drive long lines in an
analog system, you must do the same. Note that for really fast signals, digital de-
signers don’t even lay out their PC traces with square comers; they bend the foil
around the comer in a couple of 45” turns. Many digital engineers are not just bit-
pushers; they’ve been learning how to handle real signals in the real world. They are
actually pretty expert in some analog techniques, and analog engineers can learn
from them.

Perfect Waveforms Don’t Exist

Even though many digital engineers are familiar with real problems, they often
sketch the waveforms from gates and flip-flops showing nice, crisp, vertical rises and
showing the output of a gate changing at the same time as the input. But smart engi-
neers are aware that when it comes down to the fine print, they must be prepared to
admit that these waveforms have finite rise-times and delays. These nit-picking de-
tails are very important when your signals are in a hurry.
For example, if the data input of a D flip-flop rises just before you apply the clock
pulse, the output goes high. If the data input rises just after you apply the clock pulse,
the output goes low. But if the D input moves at just the wrong time, the output can
show “metastability”-it can hang momentarily halfway between HIGH and LOW
and take several dozen nanoseconds to finally decide which way to go. Or, if the data
comes just a little earlier or later, you might get an abnormally narrow output pulse-
a “runt pulse.”
When you feed a runt pulse to another flip-flop or counter, the counter can easily
respond falsely and count to a new state that might be illegal. Thus, you should avoid
runt pulses and make sure that you don’t clock flip-flops at random times. Fig 10. la
contains an example of a D flip-flop application that can exhibit this problem. When
the comparator state changes at random times, it will occasionally change at precisely
the wrong time-on the clock’s rising edge-making the output pulse narrower or
wider than normal. In certain types of A/D converters, this effect can cause nonlin-
earity or distortion. A good solution is to use a delayed clock to transfer the data into
a second flip-flop, as in Fig 10.1 b.
A glitch is an alternate name for a runt pulse. A classic example of a glitch occurs
when a ripple counter, such as a 7493, feeds into a decoder, such as a 7442. When the