Page 69 - Troubleshooting Analog Circuits
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56                            5. Preventing Material and Assembly Problems


                          boards, which scares the heck out of me. If you have to use an eyelet, don’t count on
                          it to connect the top foil to the bottom. These days, plated-through holes are quite
                          reliable, but I still like to use twg plated-through holes in parallel, whenever I have
                          room, or to put a component’s lead through the hole. It just makes me feel more com-
                          fortable. (See Chapter 13 for more comments on eyelets.)
                            More important than these layout conveniences is that your layout should not
                          interfere with and, if possible, should enhance the expected performance of the cir-
                          cuit. I try to make my layouts so the PC runs (and the metal runs on an IC chip) are as
                          short and compact as possible, especially the sensitive ones that would receive a lot
                          of noise or leakage or have a lot of capacitance, if they were longer. Otherwise, you
                          have a lot of long wire runs that turn into a whole hank of spaghetti.
                            On the other hand, sometimes we have to locate some of the components in odd
                          locations, for different reasons such as thermal or human interface-which  leads to
                          the “spaghetti syndrome.” But sometimes you have to do it-it’s  a matter of engi-
                          neering judgment, a matter of the trade-offs you have to make. Recently I was trying
                          to design a 200-MHz counter, to start and stop in less than 5 ns (Ref. 1). I was able to
                          lay out the fast 100,000-type ECL gates right close to each other, and with this close
                          layout, I was able to gate the clock counter ON and OFF very quickly, faster than 3
                          ns. Most designers of digital circuits are aware that, with high-speed logic, you can’t
                          just run the fast signals “any old way.” You have to treat these signal paths as trans-
                          mission lines and route them carefully.  So, whether with printed-circuit foils or wire-
                          wrapped conductors or IC metal runs, most digital-circuit designers have learned to
                          design the wiring of fast digital circuits so that they work well-to  avoid ringing and
                          crosstalk.
                            However, I have seen cases in which an experienced digital designer had to add a
                          few linear circuits into one comer of a mostly digital PC board. If the designer makes
                          bad guesses about how to wire an op amp, the linear circuits may oscillate  or exhibit
                          bad cross-talk or work poorly. And, the availability of wire-wrap connections makes
                          it tempting for the board designer to make a neat-looking layout with all the op amps
                          and comparators and feedback resistors and capacitors in neat rows. Unfortunately,
                          this nearness causes some critical interconnections to be a couple of inches apart, and
                          causes other signals to be bussed too closely to each other. And then the designer is
                          puzzled as to why the amplifiers and comparators are oscillating  so badly.
                            So, PC-board designers should be made aware that the layout of linear ICs can be
                          quite critical. The 2-inch spacing that you would never allow, for example, between a
                          digital IC and its bypass capacitor is the same 2-inch spacing that makes an op amp
                          unhappy when its inverting or noninverting input has to travel that distance to various
                          resistors or capacitors. As I will explain in future chapters on active-circuit trouble-
                          shooting, there are good reasons to keep those summing-point foils short, neat, and
                          compact. Meanwhile it is not fair to assume that the PC board layout-designer will be
                          able to guess which nodes are critical. The circuit-design engineer must provide a list
                          of the nodes that are critical or sensitive-a  list of large, noisy signals to keep away
                          from delicate inputs, and so forth. It’s only reasonable.
                            Some engineers like to use narrow PC foil runs, as narrow as possible. Others like
                          to use wide foils and narrow stripes of insulation. Neither one is wrong, but you
                          should be aware of the advantages of using large areas of foil when you are laying
                          out a high-power transistor or IC. The collector of a TO-92 transistor can put a lot of
                          heat down its (copper) collector lead, and an extra square inch of PC foil (on either or
                          on both sides of the PC board) can spread that heat out and help keep the transistor
                          cool. The same is true for high-power ICs: if you look at the data sheet of a medium-
                          power IC such as the LM384,  the curves show that 2 square inches of copper foil can
                          help keep the IC much cooler than minimum foil, and 6 square inches is even better,
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