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Load/store and branch instructions 65

encoded as a signed offset from the load instruction. Since instructions are four bytes
long, the label will be at an address that is a multiple of four bytes. On a binary level,
the label’s offset is encoded in 19 bits. It is then multiplied by four (shifted left by two)
and added to the program counter to obtain the label’s address.
Pseudo load: =<immediate|symbol>
This is a pseudo-instruction. The assembler will generate a mov instruction if possible.
Otherwise it will store the value of immediate or the address of symbol in a “literal
pool”, or “literal table”, and generate a load instruction, using one of the previous ad-
dressing modes, to load the value into a register. This addressing mode can only be
used with the ldr instruction. An example pseudo-instruction and its disassembly are
shown in Listing 3.1 and Listing 3.2.
Listing 3.1 LDR pseudo-instruction.

1 .text
2 ldr x0, =0x123456789abcdef0
3 ret

Listing 3.2 Disassembly of LDR pseudo-instruction

0: 58000040 ldr x0, 8 <.text+0x8>
4: d65f03c0 ret
8: 9abcdef0 .word 0x9abcdef0
c: 12345678 .word 0x12345678

3.4 Load and store instructions

The load and store instructions allow the programmer to move data from memory to registers
or from registers to memory. The load/store instructions can be grouped into the following
types:
• single register,
• register pair,
• atomic.

3.4.1 Load/store single register

These instructions transfer a double-word, single word, half-word, or byte from a register to
memory or from memory to a register:
ldr Load Register, and
str Store Register.