Page 240 - An Introduction to Microelectromechanical Systems Engineering

Key Design and Packaging Considerations 219

Wafer or Wafer-Stack Thickness

Standards in the electronic integrated-circuit industry dictate specific thicknesses for
silicon wafers depending on their diameters. For example, a standard 100-mm
(4-in) diameter silicon wafer polished on one side has a nominal thickness of
525 µm. The standard thickness increases to 650 µm for 150-mm (6-in) diameter
wafers. Wafers polished on both sides are normally thinner. Glass substrates are at
least 250 µm (10 mils) thick. Often, a stack of bonded silicon or glass wafers can
have a total thickness exceeding 1 mm, posing significant challenges for packaging
facilities. In some cases, it becomes outright impossible to accommodate such large
thicknesses. Proper communication of the thickness to the parties responsible for
packaging is imperative in order to minimize disruptions to the assembly line and
avoid unnecessary delays.

Wafer Dicing Concerns
A key highlight of MEMS technology is the batch fabrication aspect—hundreds and
thousands of identical structures or microsystems are fabricated simultaneously on
the same wafer. Dicing separates these structures into individual components (dice)
that can be later packaged. A diamond or carbide saw blade, approximately 50 to
250 µm wide, spins at high speed and cuts through the substrate that is normally
mounted and held in position on a colored “sticky tape” known as dicing tape.
Water flows continuously during sawing to cool the blade. Dicing is a harsh process
conducted in an unclean environment and subjects the microstructures to strong
vibrations and flying debris. Retaining the integrity and cleanliness of the micro-
structures requires protecting the sensitive components from particulates and liq-
uids as well as ensuring that they can survive all of the shaking.
Each MEMS design merits its own distinctive approach on how to minimize the
adverse effects of dicing. In surface-micromachined MEMS, such as the accelerome-
ter from Analog Devices, protection can mean, for example, forming shallow dim-
ples in the dicing tape and mounting the wafer upside down such that the sensitive
micromechanical structures face toward and are aligned with the dimples. Alterna-
tively, it is possible to perform the final sacrificial etch (see Chapter 3) after the dic-
ing is complete. While this postprocess approach ensures that there are no free
mechanical structures during the dicing, it implies that the microstructures must be
freed on each individual die, thus sacrificing batch fabrication for mechanical integ-
rity. This naturally increases the final fabrication cost. The fabrication process of
the Texas Instruments, Digital Mirror Device (DMD) follows this approach. The
DMD arrays are diced first, then the organic sacrificial layer on each individual die
is subsequently etched in oxygen plasma. Because the rumored selling price for each
DMD is in the hundreds of dollars, this method may be economically justified, but
accelerometers intended for the automotive market command prices of a few dollars
at most with little margin to allocate to the dicing process.
The reader will observe in Chapters 4 through 7 a number of designs incorpo-
rating bonded caps or covers made of silicon and occasionally glass, whose sole pur-
pose is to protect the sensitive micromechanical structures. These become, after the
completion of the cap, fully embedded inside an all-micromachined housing—a
first-level package. For example, the yaw-rate sensor from Robert Bosch GmbH
includes a silicon cover that protects the embedded microstructures during dicing,