Page 335 - Analog and Digital Filter Design

332 Analog and Digital Filter Design

range. This is 2n times the frequency difference in Hertz, divided by 3.2V (in
my example, the input voltage range is 0.9V to 4.1 V).

Phase Noise

The frequency multiplier circuit produces an output signal frequency that is a
multiple of the input signal. Unfortunately, the timing of the clock transitions
does not always take place at the same point relative to the phase of the input
signal. The reason for this is noise at the voltage-controlled oscillator (VCO)
input causes the frequency to instantaneously rise and fall. On average the
frequency is correct, but the period of each half cycle may be longer or shorter,
depending on whether the noise voltage is increasing or decreasing the control
potential of the VCO.

The loop filter bandwidth controls the phase noise to a great extent. Even if the
control voltage was noise free, circuitry within the VCO device adds noise and
causes jitter. In the example a CMOS logic circuit was used, but CMOS is noisy.
A bipolar oscillator should give better results. Another way to reduce phase
noise is to reduce the frequency range of the oscillator. Noise voltage will then
produce a smaller instantaneous frequency change; that is, the phase shift will
be less.

To illustrate the problem of internal VCO noise I will extend the Practical
Digital Phase-Locked Loop system described earlier. The frequency range
was 140kHz with a control voltage range of 3.2V, so a 1mV RMS (root
mean square) noise voltage will introduce an average instantaneous frequency
difference of 43.75Hz. Consider the time domain; at 5OkHz the period of the
oscillator output is 20p, and at 50,043.75Hz the period is 19.9825153ps,
which is a difference of almost 17.5ns. Since peak to peak noise can be
many times the RMS level, the timing of the oscillator output transitions
may vary from one cycle to the next. It would not be unknown for the peak
level to be five times the RMS level. This would produce a phase jitter of
87.511s when compared with the reference signal. In some applications, such as
in a communications synchronization circuit, this amount of jitter would be
unacceptable.

Capture and lock Range

The lock and capture ranges determine how well the phase-locked loop will
follow signals at the input. The range depends upon the type of phase com-
parator used and on the loop filter design. Phase and frequency detectors of the
edge-triggered type have equal lock and capture ranges.