Page 331 - Analog and Digital Filter Design

328 Analog and Digital Filter Design

approximately 12/2nf,,, when the phase margin is 45". For a value of fo = 100 Hz,
the time for a loop to reach stability will be approximately 19ms.

Rule-of-thumb values are& = fd2.5,& =fo x 3.33, andh =fo x 10. Note thatf,
is the zero frequency that must remain below the loop frequency at all times.
Using the equations to find the phase margin gives:

a = tan-'(wOT2) = tan-'(fo/f2) = tan-'(2.5) = 1.1903 rad
/3 = tan-'(woT,) = tan-'(&/&) = tan-'(0.3) = 0.29146 rad
y = tan-'(woT4) = tan-'(fo/fi) = tan-'(0.1) =0.09966 rad
$,,) = a - p - y= 1.1903 - 0.29146 - 0.09966 = 0.79918 rad
= 45.79 degrees

Time constant T1 is determined from the phase-locked loop characteristics.

ir;= Kp .a~s[cos(a>.cos(p>.cos(y)]
4n'fo'N

For a phase detector having a voltage output, the value of the phase
sensitivity is given by K,, = VCc/2n: typically 0.7958. If a charge current
output is available from the PLL device, the phase sensitivity is given by
K,, = I/2n. Hence, to find the value of TI, 4, KJR1 = I/(2n. Rl). Using values
=
(for example) KG = 2 x 10' and the feedback divider ratio N = 1000, gives TI =
142.7 ms.

Now Q, = 27&0, so in this case wo = 628.32 rads. Substituting into the above
equations, the values of T2, T3, and T4 can be found.

T, = tan(a)/wo. = tan(1.1903)/628.32 = 2.5/628.32 = 3.97898 ms.
T, = tan(p)/wo . = tan(0.29146)/628.32 = 0.3/628.32 = 0.477464 ms.
T4 = tan(y)/wG. = tan(0.09966)/628.32 = 0.1/628.32 = 0.159155ms.

First choose the value of C3 and derive the value of R3 from R3 = TJC3.
Let C3 = O.1pF and since T4 = 0.159155ms, R4 = 159.155 x 10-'?0.1 x =
1591.55Q.

Now choose the value of C1 and derive the value of R1 from R1 = Tl/C1. Let
C1 = 1pF. R1 = 0.1427/10-6 = 142.7kQ - 150kQ.

Finally, calculate the value of C2 and R2. Derive the value of R2 from R2 =
(T2 - T3)/C1= 3.501516 x 10-3/10-6 = 3502f2. The value of C2 can be found using
C2 = T3/R2 = 0.477464 x 10"/3502 = 0.13634pF.