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                             216 CHAPTER EIGHT
                             DSP can be used as a string of FIR registers and coefficient registers. Also, structures
                             are used to move data efficiently through the DSP chip as rapidly as possible. DSP pro-
                             grammers can take advantage of many library functions. Implementing a simple FIR
                             filter can be accomplished just by specifying the number of taps and the coefficients.
                             The DSP compiler takes care of the rest of the work.
                             Hardware
                             Well, enough ranting about software and hardware people. The sad truth is, we need
                             each other. Even the pure hardware implementation of FIR filters requires a significant
                             amount of software tools and programming. Prepackaged implementations of FIR fil-
                             ters are available, but not common. The most common way they are implemented is in
                             Application-Specific Integrated Circuits (ASICs) or FPGAs. FPGAs contain many reg-
                             isters and logic elements that can be configured using software. The software is typi-
                             cally written in higher-level languages like VHDL or Verilog. The VHDL code lines
                             engender tap registers, coefficient registers, and Multiply and Accumulate (MACs). The
                             entire FIR filter structure is visible right in the code itself. When the VHDL code is
                             compiled and loaded into an FPGA, the FIR filter takes on a physical instantiation.
                               Here are some web sites describing FIR filter design in such languages:

                                 www.doulos.com/fi/vhdl_models/model_9605.html
                                 www.item.uni-bremen.de/research/papers/paper.pdf/Helge.Bochnik/nato93/
                                 boc9301.pdf
                                 www.altera.com/support/examples/verilog/ver_base_fir.html


                             Testing FIR Filters
                             Several easy tests can be run on a FIR filter design when it is first tested. Some tests
                             are so simple they can be built right into the physical implementation. This allows the
                             test to be executed at a later time. The FIR filter tests are as follows:
                                 Coefficient test  Feed the FIR filter a series of data points consisting of all
                                 zeroes with a single full value in the middle of the stream. As the full value hits
                                 each FIR filter tap along the way, the output will be a serial stream equal to all the
                                 coefficients right in order.
                                 Frequency sweep To test any filter, analog or DSP, sweep it with a series of pure
                                 sine waves. The frequency response curve should be similar to that shown in the
                                 DSP design software. Further, if we continue the sine wave sweep above the
                                 Nyquist frequency, we should observe the effects of the antialias filter. If we
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