Page 39 - Building A Succesful Board-Test Strategy

What Is a Test Strategy? 25

What types of memory devices does the system contain? Read-only memory
chips (ROMs), non-volatile RAM chips (NVRAMs)? How large are the single
inline memory modules (SIMMs)? How many different SIMM configurations must
the board accommodate?
Including ASICs in a design opens up a host of additional questions. Do you
test them at all, or do you depend on device suppliers to provide working parts?
Theoretically, board and system manufacturers should be able to rely on suppliers
and forego incoming inspection of ASICs because of its prohibitive cost. On the
other hand, you do not want to build a board with parts that do not work. The
most efficient approach usually involves cooperation between parts makers and
customers. Vendors can generally test ASICs less expensively than their customers
can, and they have more experience and greater expertise in quality assurance and
failure analysis.
In addition, just-in-time manufacturing techniques include small production
lots and tight inventory control. Holding up operations to accommodate com-
ponent testing rapidly becomes unacceptable.
Regardless of who tests the parts, where do test sets come from? System
designers who are responsible for designing first-pass ASICs should propose initial
test approaches, but again final versions should represent a cooperative effort
between system designers and ASIC vendors. When presented with this recom-
mendation, one company cited an example where an ASIC vendor's final produc-
tion test provided insufficient fault coverage. In that case, the ASIC customer had
to either work with the vendor to improve the test, or, as a last resort, find another
vendor. Quality of the incoming ASIC remains the vendor's responsibility.
If manufacturing engineers do not have confidence that the incoming ASICs
work correctly, they must test the devices before board assembly. Aside from the
conventional wisdom that says isolating a fault is more expensive at the board level
than at the device level, given the complexity of today's devices, adequately testing
them on boards is, at best, very difficult. A large company with a high-volume
product may elect to set up a full incoming-inspection operation. For most smaller
manufacturers or lower-volume products, finding an independent test house to
screen the devices offers a more cost-effective alternative.
Pushing ASIC testing back to the device level and assuming that the ASICs
worked prior to board assembly simplifies board-level test considerably. It is
unlikely that a working device will develop a subtle failure. Therefore, only a limited
number of failure mechanisms need testing: Is the device still alive? That is, did
some step during handling or board assembly develop sufficient electrostatic charge
to blow it up? Can it execute some basic functions? Do all the pins work? Did some-
thing get crunched during part placement? Do all the solder joints work reliably?
Looking for a failure in bit 12 on the fourth add register in the arithmetic logic
unit (ALU) is unnecessary.
Test vectors for this sort of gross test at the board level generally represent a
subset of the device-test vectors that the ASIC vendor applies during produc-
tion. Therefore, to simplify board-test generation, system manufacturers must
have access to those device-level tests. If not, board designers or test engineers