Page 29 - DSP Integrated Circuits

14 Chapter 1 DSP Integrated Circuits

their correctness since they are described using an executable language. The top-
down approach guarantees that larger and more important questions are
answered before smaller ones.
As mentioned before, and illustrated
in Figure 1.14, a typical system design
begins with the development of a proto-
type (non-real-time) of the whole DSP
system using either a conventional lan-
guage, such as C, or, preferably, a hard-
ware description language such as VHDL.
The latter will be described in brief in sec-
tion 1.6.6.
After the validation of this initial
(often sequential) description of the DSP
system, it can be used as the basic system
description. Subsequently, the system is
hierarchically decomposed into a set of
subsystems that at the lowest level imple-
ment well-known functions. This is one of
the most important tasks in the system
design phase—to partition the whole sys-
tem into a set of realizable subsystems
and to determine their individual
specifications—because the partitioning
will have a major effect on the system Figure 1.14 Top-down design strategy
performance and cost. Typically, the new
system description, which has explicit descriptions of the subsystems, is first
derived without regard to time. However, it is advantageous to use at this stage,
for example, VHDL, instead of a conventional sequential computer language since
such languages do not have mechanisms for describing time and parallel execution
of the subsystems.
Generally, a sequential execution of the subsystems cannot meet the real-time
requirements of the application. In the next design step, called the scheduling
phase, the sequential description is therefore transformed into a parallel descrip-
tion where the subsystems are executed concurrently. In this step, synchronization
and timing signals must be introduced between the subsystems.
If a satisfactory solution cannot be found at a certain design level, the design
process has to be restarted at a higher level to ensure a correct design. Indeed, the
whole design process is in practice an iterative process. Often the whole system
design can be split into several parallel design paths, one branch for each main
block. The different parts of the system can therefore often be designed by inde-
pendent design teams.
The next design step involves the mapping of the algorithms that realize the
subsystems onto suitable software-hardware structures. This design step can be
performed using the strategies discussed in sections 1.3 and 1.4.
In the direct mapping approach, discussed in section 1.4.2, the operations are
scheduled to meet the throughput requirements and at the same time minimize
the implementation cost. Scheduling techniques for this purpose will be discussed
in detail in Chapter 7. Further, in this design step a sufficient amount of resources