Page 104 - Embedded Microprocessor Systems Real World Design
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Partial Address Decoding
                  Say  a  microprocessor with  a 20-bit  address bus  (1Mbit space)  needs an  8K x  8
                  EPROM at location FEOOO.  Decoding the entire range of addresses would require
                  that 6 bits  (A14 through A19) be decoded. If only A16 through A19 are decoded
                  using a four-input NAND gate, the EPROM will be addressed anytime the proces-
                  sor  accesses anything in  the  range FOOOO  through  FFFFF.  This works as long as
                  nothing else needs to go in that range. The EPROM may be accessed in the address
                  space starting at F0000, F2000, F4000, and so on.

                  Linear Address Decoding

                  Assume that a microprocessor with a l&bit address bus  (64K space) needs an 8K
                  EPROM and a 2K RAM. The EPROM goes at location 0. To decode this, connect
                  A15 from the processor to the EPROM -CE  input. Connect A14 through an inverter
                  to the RAM -CE  input. Now the EPROM is accessed anytime that A15 is 0, which
                  is anywhere in the lower 32K. The RAM is selected any time that A14 is  1, which
                  occurs from 4000 to 7FFF and from COOO  to FFFF. The first range also enables the
                  EPROM, causing a bus conflict. However, if the software addresses the EPROM from
                  0000 to lFFF and the RAM from COOO  to C7FF, the EPROM will be deselected and
                  no bus conflict occurs. This principle can be expanded to as many decodes as there
                  are available address lines.


                  Buffer Always Enabled

                  When using data bus buffers, it is not always necessary to enable and disable the
                  buffer’s tristate outputs. Instead, the buffer can be enabled all the time, usually by
                  grounding the enable pin, and the direction can be controlled. In this scheme, the
                  processor side of the buffer normally is the input and the peripheral side normally
                  is the output. The direction  is reversed only when the processor reads from the
                  peripheral. When using this technique, the buffer must switch directions to drive
                  the processor data bus only when the processor is not driving it and must switch
                  back only after the peripheral has stopped driving it. Otherwise, you will get bus
                  contention.



                  ~~~~~~
                   EMC Considerations


                  Most embedded systems end up in products that require certification to EMC stan-
                  dards. In the United States, the Federal Communications Commission (FCC) has
                  limits on how much RF energy a product can emit. The European Community also
                  has standards for EMC compatibility, and they include susceptibility to external RF


                  86                                              Embedded Micr@ocessm  Systems
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