Page 99 - Embedded Microprocessor Systems Real World Design
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a DMA transfer. The DMA controller requests the bus, does the transfer, and gives
                 the bus back to the processor. The DMA  controllers are programmable and can
                 transfer data from memory to memory, from memory to I/O, from 1/0 to memory,
                 and from 1/0 to I/O.  Most  importantly, all the arbitration is handled inside the
                 microprocessor, which saves on hardware and ensures that all the timing is correct.
                 In addition, an internal DMA controller can usually transfer data to and from inter-
                 nal RAM (internal to the CPU IC), which an external DMA controller cannot do.
                    DMA requests can come from a source that needs to send data (such as a UART
                 that has received a byte and needs to transfer it to memory) or from a destination
                 device that needs to receive data (the same UART may have just transmitted a byte
                 and  needs a new  one). In  some systems, it does not  matter whether  the  DMA
                 requester is a source or destination device. In other cases it does.
                    The  80186/80188  DMA  controllers  support  either  source  or  destination
                 requests, which are referred to on the datasheet as source or destination synchro-
                 nization. In practice, either device can be the requester since source/destination
                 synchronization is programmed into the DMA controller by the firmware. However,
                 the choice of source versus destination synchronization affects the timing. Source
                 synchronization permits  faster  transfers but  requires that  the  DMA  request  be
                 removed before the end of  the DMA  write cycle. Destination synchronization is
                 slower but has more relaxed timing for removal of the DMA request.
                    The Motorola MCF5407 ColdFire processor provides an internal four-channel
                 DMA controller. Two  channels support DMA requests from external devices and
                 two permit the internal UARTs to transfer data to memory.
                    As mentioned earlier, DMA  can be used for dynamic memory refresh. This is
                 accomplished by  using a timer to request a periodic DMA cycle at the memory
                 refresh rate. The DMA  controller is programmed to read the memory and write
                 the contents to a nonexistent memory or 1/0 location. The result is a periodic
                 read from memory that refreshes memory contents.




                  Watchdog Timers


                 A  microprocessor executes instructions from memory. If  a nearby electrical dis-
                 charge occurs, the processor data bus may be momentarily upset, and the proces-
                 sor can get a bad byte from the PROM.  Or a software bug can result in  a stack
                 overflow, and the processor gets garbage when it tries to return from a subroutine.
                 In either case, the processor will usually go “into the weeds,” which is a shorthand
                 way of saying that it will begin executing code in some unpredictable way, usually
                 resulting in a system crash.
                    If this happens to the keyboard controller in your PC, you can just turn the power
                 off and back on, and everything will  be fine. If  it happens to the processor that


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