Page 97 - Embedded Microprocessor Systems Real World Design

that addresses memory is incremented at the end of the cycle, so the next byte
received will be placed into the next memory location. Transferring data from
memory to the UART transmitter works the same way except that the memory read
cycle occurs first.
In this example, the DMA controller performs a read and a write cycle during
one DMA HOLD/HLDA cycle. You can also design the system so that the DMA
controller performs one HOLD/HLDA cycle for each read and write.
Another technique is called a “flyby” transfer; it is used by the DMA controller
in desktop PCs. This method works only if the CPU and 1/0 bus support a sepa-
rate 1/0 space with separate -RD and -WR signals for 1/0 transfers. On the orig-
inal PC, for example, the memory read and write signals were -MEMR and
-MEW. The 1/0 read and write cycles were -1ORD and -1OWR. To perform a
flyby transfer, the DMA controller will generate the -1ORD signal to the peripheral
and then perform a memory write cycle (-MEW low) while the -1ORD signal is
still active. This permits the entire DMA transfer to be performed in one cycle, but
it requires that the 1/0 devices recognize a DMA cycle and respond appropriately.
Since the address presented to the bus during a flyby cycle is the memory address,
the I/O peripheral must ignore the address and rely only on the DMA acknowl-
edge and the control signals to drive data onto the bus.
Whether the DMA device is a DMA controller or another CPU, the DMA device
must generate the address, data, and control signals just like the CPU does in order
to transfer data to and from memory. This may have an impact on system design.
For example, you might design a peripheral circuit that uses ALE in some way. In
that case, the DMA device must also generate an ALE signal or the circuit will not
work as intended. If you implement DMA with a controller that does not generate
ALE (or generates it with significantly different timing), you must synthesize the
ALE signal using timing logic. Similarly, read and write strobes must have timing
sufficiently similar to the timing produced by the CPU that the memory and periph-
erals will respond correctly.

DMA Timing Issues
One common mistake in designing with DMA is illustrated by the following
scenario:
Processor 2 requests bus from Processor 1.
Processor 1 gives up bus.
Processor 2 does whatever DMA operation it wants to do.
Processor 2 notifies Processor 1 that DMA is done.
Processor 2 requests bus from Processor 1 again. Sees bus acknowledge still
asserted, takes bus.
Processor 1, still coming out of first DMA acknowledge state, takes the bus.
Bus contention or garbage data transfer results.

Hardware Design 1 79