Page 94 - Embedded Microprocessor Systems Real World Design

disabled (driven to the high-impedance state) by driving -0E high. The upper 8
address bits are driven with an unlatched tristate data buffer. In both cases, the
HLDA signal asserted by the CPU disables the buffer outputs.
To avoid bus contention, the bus buffer used by the DMA device must not drive
the address bus until after the HLDA signal has disabled the CPU buffers, and it
must stop driving the bus before the CPU drives HLDA back low. The diagram also
shows pullup resistors on the -RD and -WR signals after the buffers. These prevent
the signals from going to an invalid state and possibly affecting memory during the
brief interval when neither the CPU nor the DMA controller is driving the signals.
Most systems that use DMA will need some type of pullup or termination on control
lines such as -RD, -WR, -DS, and so on.
This example is specific to the 80188 and shows only 16 address bits for sim-
plicity. An application using a wider address bus would, of course, require addi-
tional buffers for the extra bits. The external buffers shown in the example may
not be required if you don’t need the external address latches and if both the CPU
and DMA device have sufficient drive capability for everything on the bus.
Other CPUs that support external DMA have similar arrangements to disable
external buffers. The Intel 80C960 family uses a HOLD/HLDA scheme that is
nearly identical to the 80188, although the clocks are considerably faster. In all
cases, it is up to the designer to make sure that the DMA device does not drive the
address and data buses until the CPU has tristated its drivers.

DMA Controllers

In a DMA scheme, the second processor may not be a processor but instead a ded-
icated DMA controller. This peripheral device takes control of the bus but does no
actual processing of instructions. Instead, the DMA controller performs memory
and 1/0 read and write cycles to move data between another peripheral device and
the microprocessor’s memory. A DMA controller contains counters that automati-
cally increment to the next address after each transfer so blocks of memory can be
moved. An example DMA controller would be the one in your PC that moves data
from the hard disk controller into memory. DMA controllers permit the micro-
processor to be performing some other operation while a data transfer happens
in the background. The microprocessor just sets up the DMA and processes the
entire block of data when the transfer is complete. A DMA controller is typically
configured to generate an interrupt when the DMA transfer is complete. Figure
2.24 shows how a DMA controller could be used to transfer data to and from a
peripheral device such as a UART.
In Figure 2.24, the UART generates a DMA request when a byte of data is
received. The DMA controller requests the bus and, when the bus is granted, it per-
forms a read from the UART address, followed by a write to memory. The counter

Hardware Design 1 77