Page 304 - Embedded Microprocessor Systems Real World Design

grammed. Typically, programs that are not at the supervisor level cannot execute
certain instructions, such as instructions that disable interrupts or modify the inter-
rupt vector table.
As an example, let’s take an overview look at the memory management scheme
used by Intel for the x86 family. The Intel memory management scheme is an out-
growth of the original 8086 segmentation architecture.

Segment Registers Segment registers were introduced with the 8086 to permit
the l6bit processor to access up to a megabyte of memory (which requires 20
address bits). The 1Gbit segment register contents are shifted left four places and
added to the l6bit offset to make a 20-bit address. The memory thus is divided
into 64K segments. If a program wants access to two memory locations that are
more than 64K apart, two different values must be used in the segment register to
do so. Similarly, if the program itself is bigger than 64K, the segment register that
points to the code area must be changed when the program rolls over or jumps
into a section of code that cannot be reached with the current segment register
and program counter. For example, if the code segment register contains COO0 and
the program counter contains FFFF, the current instruction will come from the
absolute address CFFFF. You would expect the next instruction to come from
D0000, but that is not what happens. Instead, the PC rolls over to zero while the
code segment stays the same, so the next instruction comes from COOOO. The code
segment register must be changed to reach anything above D0000.
The original 8086 provided four segment registers: code segment, data segment,
stack segment, and extra segment. With the introduction of the 386 processor, a
new method was needed. The 386 is a 32-bit machine, with a 32-bit address bus. To
accommodate this architecture, the segment registers in the 386 (and above)
processors are 32 bits wide and point to a table of descriptors. When the CPU wants
to access memory, the segment (now called a selector) register is used to obtain a
64bit entry from the descriptor table. This entry contains:
The absolute 32-bit start address of the segment
The upper limit of the segment
The status, privilege level, segment type, whether the segment is present, and
the like

Thus, a program can be loaded anywhere in memory; accesses to memory
(including code, data, and stack) are translated into absolute 32-bit addresses using
the descriptor table.

Privilege Levels The Intel MMU provides for four privilege levels. Level 0 is the
highest level and permits access to anything in the system, including the MMU itself
and all instructions in the instruction set. The operating system kernel will be at
level 0.

Advanced Microprocessor Concepts 285