Page 299 - Embedded Microprocessor Systems Real World Design

A microprocessor may contain multiple PLLs to generate more than one fi-e-
quency. The SC520 has a PLL that generates 1.1882MHz (for the programmable
timers) and 18.432MHz (for the UARTs) from the 32.768kHz input. Another PLL
produces 66MHz for the SDRAM interface from the 33MHz input. The CPU core
has a PLL that multiplies the 33MHz input crystal by three or four to produce a
100MHz or 133MHz CPU clock.

Multiple-Instruction Fetch and Decode

With the addition of onchip cache memory to some microprocessors, a secondary
performance improvement is possible. It is possible to build a microprocessor
with a 32-bit interface to external memory, but a 64 or 128-bit interface between
the internal cache memory and the internal CPU core. Figure 11.7 shows this
arrangement.
Because the internal bus that interfaces the cache memory to the CPU is wider
than the CPU word, it is possible to transfer multiple instructions to the CPU at
once. With parallel hardware, the CPU can decode more than one instruction
at a time, resulting in a very high level of performance. The Intel i960 does this,
as does the Motorola Power PC. Of course, this greatly increases CPU complexity,

32-BIT
EXTERNAL MEMORY

1
I I
I I
I
I I
I I
I
128-BIT I
INTERNAL BUS I
I
I I
I I
I
INTERNAL CPU CORE I
I
I I
............................ I
I
MICROPROCESSOR IC
Figure 11.7
Wide Cache Memory.

280 Embedded Microprocessor Systems