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with fast programmable logic or custom ICs. One advantage to SDRAM is the syn-
chronous nature of the interface. Traditional DRAM requires delay lines or other
timing devices to get the -RAs and -CAS strobes correct. SDRAM synchronizes
everything to the clock signal, which is a convenience since the control logic usually
is synchronous anyway.
Some microprocessors, such as the AMD ElanSC520 microcontroller, include an
SDRAM interface on-chip.

High-speed, High-Integration Processors and Multiple Buses

Although the interfacing techniques introduced in Chapter 2 apply across all speed
ranges, some special considerations are in order for interfaces to very fast pro-
cessors. The AMD Elan SC520 is one example. The SC520 integrates a 586 CPU
core with a number of peripheral functions. One is a fast interface to external flash
memory. The 586 flash memory interface can run at 33 MHz, performing one fetch
from the flash every 30ns. Because most flash memories cannot operate at this
speed, the CPU needs wait states to access the flash. It might seem reasonable to
simply run the CPU at a slower clock and avoid wait states. However, the SC520 has
other integrated interfaces, including an SDRAM interface. Operating the flash
with wait states allows the SDRAM to run at full speed. In many cases, when using
a PCcompatible processor like the SC520, the flash is used only when starting the
system; normal operating code is stored in RAM.
Figure 11.5 is a block diagram of the Intel i960 VH processor. The i960 is a high-
performance microprocessor family. The VH version has two external buses: a local
memory bus and a peripheral component interconnect (PCI) bus. The PCI bus is
a standard interface bus in the IBM-PC world. The i960 VH incorporates a PCI con-

EXTERNAL MEMORY
f

Figure 11.5
Intel i960 VH.

Advanced Microprocessor Concepts 277