Page 291 - Embedded Microprocessor Systems Real World Design

address in anticipation of the branch being taken. If the branch is conditional and
not taken, then the new instructions are discarded and prefetching resumes from
the addresses following the branch instruction. Of course, this type of decoding
has limitations. Suppose that a branch instruction uses an indirect address, con-
tained in a register, and the register contents depend on an instruction still in the
pipeline. Obviously, the pipeline logic-for any processor-cannot prefetch data
because the destination address is not known.

Interleaving

Interleaving is used to allow a fast CPU to access slower memory without wait states.
Figure 11.1 shows a simple timing diagram that illustrates the concept of inter-
leaving. In this example, an Intel-type bus was chosen because the ALE signal
provides a reference for the processor cycles.
Two memories are shown in the figure. Each has an access time longer than the
bus cycle time. Ordinarily, this would require the insertion of wait states. However,
if each memory is accessed on every other cycle, the two memories together can
keep up with the CPU. Each memory access starts in a cycle when the other memory
is being read. In Figure 11 .l, Memory 1 is accessed on every even-numbered address
and Memory 2 is accessed on odd-numbered addresses.
Interleaving works only as long as the processor executes sequential address
cycles. The access time for one memory device starts in the bus cycle for the other
device; thus, the next address for each device must be predictable. In the example
shown, the CPU is accessing a hex address of AAOO then AAOl then AA02 (these
are just arbitrary addresses chosen for this example). After reading location AA02,
the processor jumps to AA14. This memory access cannot be interleaved because
the new address could not be predicted, so wait states must be inserted so that the

-ALE n n n n

ACCESS TIME
MEMORY 1 I I I
ACCESS TIME
MEMORV? I I I

CPU

Figure 11.1
Interleaving.

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