Page 290 - Embedded Microprocessor Systems Real World Design

Advanced Microprocessor

Concepts

This chapter provides an overview of some features that are used to improve
processor performance or to solve certain design problems.

Pipeline (Prefetch) Queue

To speed execution, some processors implement a pipeline, sometimes called a
prejetch queue. This is because many CPU instructions are fairly complex, taking
many clock cycles to perform. Multiply and divide instructions are good examples.
While the processor is executing multipleclock instructions, the bus normally is
idle. In a processor with a pipeline, the bus logic goes ahead and gets the next few
instructions in preparation for execution. The Intel 80186/188 implements a
pipeline by having the execution unit (EU) separate from the bus interface unit
(BIU). While the EU is executing instructions, the BIU continues to fetch new
instructions until the queue is full. If the next instruction in the pipeline happens
to be one that can be executed very quickly, the one following already is in the
pipeline and need not be fetched from memory.
A pipeline architecture keeps the CPU execution speed from being bogged
down by slow memory. While the CPU is executing multipleclock instructions,
the pipeline uses those clock cycles to fill up with instructions. However, the average
rate of instruction execution cannot exceed the memory bandwidth, or the
pipeline will never get ahead of the CPU and so provides no advantage.
The Motorola Coldfire CPU series takes the pipeline concept further. A draw-
back to a pipeline architecture is that, if a branch instruction is executed, all the
prefetched instructions must be discarded and the pipeline refilled from the new
address.
The MCF5307 is a 32-bit, Coldfire-family processor that fetches and partially
decodes the instructions in the pipeline. If the decoding logic detects certain
branch instructions, the pipeline will begin fetching instructions from the new

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