Page 293 - Embedded Microprocessor Systems Real World Design

I CYCLETIMEOR I

NORMAL DRAM TIMING I PRECHARGE I
I I
ADDRESS INPUTS R OW X COLUMN X ROW XCO L U MN
-RAS
-CAS
DATA

PAGE MODE TIMING
ADDRESS INPUTS 4 ROW X COLUMN XCOLUMN X COLUMN X ROW X COLUMN >
-RAS
-CAS r r
DATA

Figure 11.3
Burst Mode DRAM Access.

bytes can be read much more quickly than the first location. Any location in the
selected row can be accessed in this way.
As soon as the CPU needs information from a different row, the -RAS line must
be cycled and a new row address loaded. The access time for the first read from
the new row is the -RAS access time, but subsequent reads from that row can be
performed using burst mode access. A memory with a lOOns -RAS access time
typically would have a -CAS burst access time of around 60ns. To take advantage
of burst mode, the address decoding hardware must detect when the address
changes to a different row (because the address bits from the CPU that make up
the row address change). The -RAS signal must be cycled with the new row address.
The first memory access is governed by the -RAS access time, and so the first bus
cycle from the new row must be extended with wait states.
There are other enhancements to the page mode of operation, such as a fast
page mode and extended data output (EDO) . These all enhance performance by
changing the burst mode timing, essentially making the -CAS access time shorter
so that successive burst cycles are faster.

SDRAM

Synchronous DRAM (SDRAM) is a new type of DRAM that is optimized for high-
speed microprocessors such as 586 and Pentium-class CPUs. SDRAM is a DRAM,
and so it must be refreshed to retain the memory contents. However, synchronous

274 Embedded Micropocessar Systems