Page 302 - Embedded Microprocessor Systems Real World Design

of the breakpoint. This is an unsegmented, 32-bit address (if you do not know
what unsegmented means, do not worry about it; it is a Eunction of the x86
architecture).
Register DR7 controls what type of breakpoint is executed. Each address
register has two LEN (length) and two R/W bits; the encoding of the LEN and
R/W bits is shown in Figure 11.8.
The L&L3 and GO43 bits individually enable the four breakpoints. L&L3 are
used for local breakpoints (cleared after a task switch) and GO43 are used for
global breakpoints, which are not cleared after a task switch. This is needed because
a task switch may put something else in the memory area pointed to by the address
register, and the breakpoint would be invalid. Debug features such as these permit
a software debugger to simulate some of the features of an incircuit emulator.
A breakpoint can be executed if the processor writes to certain 1/0 addresses, for
example, or if a particular variable is accessed.
The x86 family are not the only processors with onchip debug features. Most
high-performance 32- or 64bit processors include some type of on-chip debug.
Motorola uses a method called background &buggzng mode (BDM) in some of its
processors. BDM allows an external host PC (with appropriate software, of course)
to monitor and control the target CPU. BDM uses three processor pins: a clock,
data in, and data out. These pins perform more than one function, depending on
the mode of the BDM interface. When transferring data, the BDM pins function
similar to an SPI port. The BDM data word transferred to the PC is 17 bits long.
BDM permits the user to read and write registers, read and write memory, and
perform other basic debugging functions. Unlike the Intel scheme, BDM does not
support breakpoints or other emulation-like features.
The Motorola MC68EZ328 has on-chip debug hardware that includes a single
execution breakpoint and a single bus-cycle breakpoint. The execution breakpoint
hardware generates a breakpoint when a specific address is executed. A buscycle
breakpoint is generated when a read or write is performed to a specific address.
Using the on-chip debug hardware requires a software monitor (debugger)
program to communicate with the host and to set up the internal breakpoint
registers. Having more than one instruction and one bus-cycle breakpoint requires
external hardware.
In the past, onchip debugging resources were available only on 16- to 64bit
microprocessors, not on smaller microcontrollers. For many microcontrollers, the
on-chip debugging circuitry would be a significant portion of the IC die. However,
Microchip has started adding in-circuit debugging to the PIC processors. The PIC
16F877 has added on-chip circuitry that permits a breakpoint to be set and memory
to be examined. Compared to the resources on a Pentium or Power PC, these may
seem inadequate. However, it is a big leap from where microcontroller debug was
in the past. And since microcontrollers often are used in simple applications, exten-
sive debug support is often not needed. A memory dump feature may be all that

Advanced Microprocessor Concepts 283