Page 356 - Embedded Microprocessor Systems Real World Design

The timing logic is a complex digital system. It controls the following functions:
Decoding the opcode in the instruction register.
Selecting which source will be passed to the external address bus (based on the opcode) .
Timing the external /READ and /WRITE signals and determining (based on the opcode)
whether the external bus cycle will be a read or write cycle.
Remembering whether the contents of the instruction register are an opcode or data that
need to be put someplace.
Determining (based on the opcode) which register in the register bank will provide an
input to the ALU and which register will be clocked with the data on the ALU result bus
at the end of the instruction (accumulator, register bank, IAR, or PC) .
Determining (based on the opcode) which ALU operation will be performed.
Incrementing and loading the program counter.
Finally, we look at the issue of how the two external devices knew to what addresses to
respond. Real memories have read and (for writable memories) write inputs. They also have
a signal that selects the memory. This signal can be generated by logic that decodes the
address bus. In a simple system like this, the memories could just use the highest address bit
(A15), as there are only two devices. The control store would respond when A15 is low, and
the read/write memory would respond when A15 is high. In a more complex system, addi-
tional gating logic decodes the address bus and generates select signals for all the external
devices.

Addressing Modes

Here we consolidate the various methods used to address memory in a microprocessor
system, including those we already have looked at. Figure D.8 illustrates these addressing
modes. For this section, we assume we have a simple microprocessor like the one in Figure
D.7, with a l6bit data path and 64K memory space. We look at the effects of various address-
ing and branching modes on the processor program counter (PC in the diagram) and on
two internal registers, RO and JAR.
In the example shown in Figure D.8, immediate data follows the instruction opcode in
memory. Instructions that need no additional data are followed by another opcode. It is up
to the microprocessor timing logic, which decodes the opcode, to remember that the
following byte is data and not another opcode. For these examples, we do not worry about
what the specific opcode values are, just what the opcodes do.

Direct Addressing

In direct addressing, the instruction contains the information that will be used. In the
example, the instruction opcode is followed by a data value that is loaded into the IAR. In
this example, the opcode (at location 0000) says, “Load the immediate data value (follow-
ing the opcode) into register IAR.” The data value following the opcode (0010) is loaded
into the IAR.

Appendix D 337