Page 354 - Embedded Microprocessor Systems Real World Design

The instruction register receives information from the external control store and
memory. Instructions as well as data are stored here.
The indirect address register was not in the simple processor we looked at earlier. The
indirect address register is a register that can be loaded with the results of an ALU opera-
tion. The output of the indirect address register drives one of the address mux inputs.
The address mux is a device with three 16-bit input buses, one output bus, and control
inputs. The address mux is controlled by the timing logic and can place the program counter
contents, the indirect register contents, or the instruction register contents onto the 16-bit
external address bus.
The data out register just captures the contents of the ALU result bus to drive the exter-
nal data bus for external write operations. This allows data to be written to the external
memory.
Finally, the program counter is just like the program counter in the simple micro-
processor, but it has the ability to be loaded from the ALU result bus.
This microprocessor has three external connections: a 16-bit address bus, a 16-bit data
bus, and a control bus that consists of select signals for the external control store and the
external memory. On a typical microprocessor, the individual address lines would be A0
through A15 and the data lines would be DO through D15. Note that the address bus is
output only, but the data bus can both send data from the microprocessor and receive data
from the external devices.
The external control store is just like the control store in the simple system, but it is
outside of the microprocessor chip. The external memory is readable and writable. The
control bus consists of two signals, /READ and /WRITE (the slash, /, indicates that the
signals are true when low).
Figure D.7 also shows a timing diagram of how this microprocessor accesses the two exter-
nal devices. Say that the program counter (PC on the diagram) starts out at location 0001.
The timing logic, knowing that an instruction needs to be fetched, sets the address mux to
place the contents of the program counter on the external address bus. After some setup
time, the /READ signal is driven low, also controlled by the timing logic.
When the address was placed on the bus, the control store recognized that it was being
selected. For simplicity, say that the control store recognizes any address from 0000 to 7FFFh,
and the memory recognizes any address from 8000h to FFFFh. For now, ignore how the two
devices know to which address to respond. When the /READ signal goes low, the control
store places the contents of location 0001 onto the external data bus, and the data are
clocked into the instruction register at the end of the bus cycle. The program counter also
is incremented so it now contains 0002.
Say that this instruction opcode tells the processor to get the 16-bit word of memory
pointed to by the indirect address register (IAR) and load it into one of the registers in the
register bank. The timing logic decodes the 16-bit value in the instruction register (the one
loaded from address 0001 in the control store) and initiates this operation. First, the address
mux is configured to pass the contents of the IAR register onto the external address bus.
Say this address is A105h. The external memory recognizes this address so when /READ
goes low, the memory places the contents of A105h onto the data bus. At the end of the bus
cycle, the data is clocked into the instruction register. Now the next location in the program
counter is passed to the bus and the contents of that location in the control store are clocked

Appendix D 335