Page 350 - Embedded Microprocessor Systems Real World Design

output
We are almost finished with this example, but there is one more step. We have a machine
that can execute up to 1024 instructions (10-bit program counter), but what do we do with
the results? Figure D.6 shows a final addition to the machine that adds a simple output
scheme. This change adds a bank of four output registers. If the ALU has &bit inputs and
outputs, this bank of registers provides 8 x 4 or 32 bits of output. The outputs from the
timing logic that control clocking into the Y and Z registers are expanded to add clocks
to the control register. We can control the added outputs by making the %bit field that
controls which Y or Z register gets the ALU output into a 4bit field. The control store bit
definition now looks like this:
Bits 0, 1: Select ALU function (00 = addition, 01 = negation, 10 = AND, 11 = OR)
Bits 2, 3: Select Z-register (00 = ZO, 01 = 21, 10 = 22, 11 = 23)
Bits 4, 5: Select Y-register (00 =YO, 01 = Y1, 10 = Y2, 11 = Y3)
Bits 6, 7, 8, 9: Select which register the result will be clocked into:
0000 = zo, 0001 = z1,0010 = 22,0011 = 23
0100 =YO, 0101 = Y1,OllO = Y2,0111= Y3
1000 = ORO, 1001 = OR1, 1010 = OR2, 1011 = OR3
Plus the 10 branch address bits and one branch control bit.
In a similar way, we could expand the bit fields that select the Y or Z inputs to the
ALU so that we could enable one or more &bit tristate buffers instead of the internal
registers. This would give the machine the ability to input information from the outside
world.
Now we have a complete, although very simple, microprocessor. A real microprocessor
works much the same way, but it includes the following improvements:
Much more complex, capable ALU functionality. This typically includes more logic
functions such as exclusive OR, logical shifts, and other capabilities.
A larger program counter, 16 to 64 bits wide. (However, some microcontrollers with small
internal PROMS may only have a 10- or 12-bit program counter, like our example.)
More complex branching conditions. These might include branching on overflow, branch-
ing on ALU carry, branching on some input bit being 1 or 0, and so on.
More complex control store definitions. Our simple machine used a fixed-control-bit
definition. For example, bits 2 and 3 always define which Z register will be used. A real
microprocessor might have instructions that do not use some registers. An immediate
instruction might load data directly from the control store to one of the registers. None
of the bits that select which register drives the ALU is needed, nor are the ALU control
bits needed. So, for those instructions, these bit definitions would change. A branch
instruction might use the Z-register bits to determine what branch condition to test for
(carry, no carry, zero, nonzero, and so on). We looked at a simple case of this, with the
possibility of allowing the control store branch address field to double as a data value for
nonbranching instructions. Making the control bits perform different functions for
different instructions complicates the timing and control logic but allows the control
store word to be implemented with fewer bits.

Appendix D 331