Page 355 - Embedded Microprocessor Systems Real World Design

into the instruction register. At the same time, the contents of the instruction register, which
was loaded from memory on the previous bus cycle, are clocked into whatever destination
register they are supposed to go to.
This simple example is very similar to a real microprocessor. A few things are worth
noting:

First, the external address bus is 16 bits, so it can access 65,536 (64K) locations. In our
example, the control store uses half and the memory uses half, so each has 32,768 loca-
tions. However, there is no reason the control store could not be 48K in size and the
memory 16K or vice versa.
The control store and the memory are identical except that the memory can be written
to as well as read from. This means we could use one device to do both functions as long
as we do not overwrite the area where the instructions are stored. Instead of a 32K control
store and a 32K memory, we could use a 64K memory with the instructions stored in the
lower half and data stored in the upper half. In fact, this is what many systems do, includ-
ing the PC you probably have on your desk. The PC has a small amount of memory that
can only be read (like our control store) and a huge amount of memory that can be both
read and written. The read-only memory is used to start everything, and then everything
the computer needs to run is loaded from the disk drive and stored in the read/write
memory.
The external data bus can be either the contents of the IAR register, the contents of the
program counter, or the contents of the instruction register. This implies that we can
perform only one operation at a time (get an instruction, get data, write data, and so on).
It is possible to build a microprocessor with multiple address buses that can perform more
than one kind of bus cycle at a time to different storage devices.
Although we did not walk through an example, the program counter can be loaded from
the ALU output or from the instruction register. Thus, we could add two numbers and
make the sum the address of the next instruction we execute. Or, we could have an instruc-
tion that is followed by a data byte, and the data byte is the new starting point for the
program counter. This gives the microprocessor branching capability like the simpler
machine we looked at earlier. We even could have an instruction that uses the contents of
the IAR to get a data value that is the address of the next instruction. This would be an
indirect branch instruction.
The contents of the instruction register can be placed on the ALU bus and loaded into
one of the registers or the program counter. This implies the ability to tristate the outputs
of the ALU. In a real microprocessor, the tristate function probably would be performed
by a multiplexer like the address mux, because tristating buses inside the chip requires
more logic. But the effect is the same.
The second bus cycle used the contents of the IAR to address the external memory device.
If the IAR had held a value between OOOOh and 7FFFh, the control store would have been
selected instead, and we would have read the data from there. So we could dedicate a
portion of the control store to a table of data. This data could be almost anything that is
constant, such as a degrees-tmsine conversion table or a table of atmospheric pressure
versus altitude.

336 Appendax D