Page 41 - Engineering Digital Design

12 CHAPTER 1 / INTRODUCTORY REMARKS AND GLOSSARY

Diode: a two-terminal passive device consisting of a p-n junction that permits significant
current to flow only in one direction.
Diode-transistor logic: logic circuits consisting mainly of diodes and BJTs.
Direct address approach: an alternative approach to FSM design where PS feedback is
direct to the NS logic.
Disjoint: as used in "mutually disjoint" to mean a set of p-terms whose ANDed values
taken two at a time are always logic zero; or a set of s-terms whose ORed values taken
two at a time are always logic one.
Distributed path delays: a notation in which a path delay is assigned to each gate or
inverter of a logic circuit.
Distributive law: The dual of the factoring law.
Divide-by-w counter: a binary counter of n states whose MSB output divides the clock
input frequency by n.
Dividend: the quantity that is being divided by the divisor in a division operation.
Divider: a combinational logic device that performs the binary division operation.
Divisor: the quantity that is divided into the dividend.
DLP: digital light processing.
DMUX: demultiplexer (see decoder).
Domain: a range of logic influence or control.
Domain boundary: the vertical or horizontal line or edge of a K-map.
Don't care: a non-essential minterm or maxterm, denoted by the symbol 0, that can take
either a logic 1 or logic 0 value. Also, a delimiter 0 that, when attached to a variable or
term, renders that variable or term nonessential to the parent function.
DPU: data path unit; also data processing unit.
Drain: one of three terminals of a MOSFET.
DRAM: dynamic RAM.
Driver: a one-input device whose output can drive substantially more inputs than a stan-
dard gate. A buffer.
DTL: diode-transistor logic.
D-trio: a type of essential hazard that causes a fundamental mode machine to transit to
the correct state via an unauthorized path.
Duality: a property of Boolean algebra that results when the AND and OR operators (or
XOR and EQV operators) are interchanged simultaneously with the interchange of 1's
and O's.
Dual-rail systems: as used in this text, a system of split signals in an ALU configuration
that permits a completion signal to be issued at the end of each process, be it arithmetic
or logic.
Dual relations: two Boolean expressions that can be derived one from the other by duality.
Duty cycle: in a periodic waveform, the percentage of time the waveform is active.
Dyad: a grouping of two logically adjacent minterms or maxterms.
Dynamic domino logic: buffered CMOS logic that requires complementary precharge
and evaluate transistors for proper operation.
Dynamic hazard: multiple glitches that occur in the output from a multilevel circuit
because of a change in an input for which there are three or more asymmetric paths
(delay-wise) of that input to the output.
Dynamic RAM: a volatile RAM memory that requires periodic refreshing to sustain its
memory.