Page 46 - Engineering Digital Design

1.4 GLOSSARY OF TERMS, EXPRESSIONS, AND ABBREVIATIONS 17

Indirect address approach: an alternative approach to FSM design where PS feedback
to the NS logic is by way of a converter for the purpose of reducing MUX or PLD
size.
Inertial delay element: a delay circuit based mainly on an R-C component.
Initialize: to drive a logic circuit into a beginning or reference state.
Input: a signal or line into a logic device that controls the operation of that device.
Input/state map: a K-map, with inputs as the axes and state identifiers as cell entries,
that can be used to determine if the sum rule and the mutually exclusive requirement of
any state in an FSM have been violated.
Integrated circuit (1C): an electronic circuit that is usually constructed entirely on a
single small semiconductor chip called a monolith.
Intersection: AND operation.
Inversion: the inverting of a signal from HV to LV or vice versa.
Inverter: a physical device that performs inversion.
Involution: double complementation of a variable or function.
I/O: input/output.
IOB: I/O block.
Irredundant: not redundant, as applied to an absolute minimum Boolean expression.
Irrelevant input: an input whose presence in a function is nonessential.
Island: a K-map entry that must be looped out of a single cell.
Iterative: repeated many times to achieve a specific goal.
JEDEC: Joint Electron Device Engineering Council as it pertains to PLD programming
format.
JK flip-flop: a type of flip-flop that can perform the set, reset, hold, and toggle operations.
Juxtapose: to place side by side.
Karnaugh map (K-map): graphical representation of a logic function named after M.
Karnaugh (1953).
Keyword: a word specific to a given HDL.
Kirchhoff's current law: the algebraic sum of all currents into a circuit element or circuit
section must be zero.
Kirchhoff s voltage law: the algebraic sum of all voltages around a closed loop must be
zero.
K-map: Karnaugh map.
LAC: look-ahead-carry (see also CLA).
Large-scale integrated circuits (LSI): 1C chips that contain 200 to thousands of gates.
Latch: a name given to certain types of memory elements as, for example, the D latch.
Latency: the time (usually in clock cycles) required to complete an operation in a se-
quential machine.
LCA: logic cell array.
LD: mnemonic for load.
Least significant bit (LSB): the bit (usually at the extreme right) of a binary word that
has the lowest positional weight.
LED: light-emitting diode.
Level: a term used when specifying to the number of gate path delays of a logic function
(from input to output) usually exclusive of inverters. See, for example, two-level logic.
Level triggered: rising edge triggered (RET) or falling edge triggered (FET).
Linear state machine: an FSM with a linear array of states.